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datasheet four channel hd audio codec optimized for low power/low cost 92HD95 1 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 description the 92HD95 is a low power optimized, high fidelity, 4-channel audio codec compatible with intel?s high defini- tion (hd) audio interface. the 92HD95 provides high qual- ity, hd audio capability to notebook and desktop pc applications. features ? 4 channel (2 stereo dacs, 2 stereo adcs) with 24-bit resolution ? microsoft wlp premium logo compliant ? 2w(4ohm)/1w(8ohm) class-d stereo btl amplifier at <1% thd+n and 5v ? selectable frequency hardware high-pass filter for speaker protection. ? 10 band hardware parametric equalizer (5 bands per channel) for speaker optimization in all operating scenarios ? hardware compressor limiter allows higher average volume level without resonances or damage to speakers. ? integrated class-g true capless stereo headphone amplifier with charge pump/ldo ? 4 analog ports with port presence detect (3 single ended, 1 btl) ? combo jack support allowing for dual-function headphone and headset detection ? 2 voltage adjustable vref_out pins for microphone bias ? 2 digital microphone inputs (4 mic support) ? microphone mute input ? selectable 1.5v and 3.3v hda signaling ? internal dvdd ldo voltage regulator ? supports runtime d3 (rtd3) low power mode ? capable of mslync compliance ? full hda015-b and eup low power support ? audio inactivity transitions codec from d0 to d3 low power mode ? resume from d3 to d0 with audio activity in < 10 msec ? d3 to d0 transition with < -65db pop/click ? port presence detect in d3 with or without bit clock ? pc beep wake up in d3 ? additional vendor specific modes for even lower power ? 3.3 v analog power supply ? digital and analog pc beep to all outputs ? 40-pin 5mm x 5mm qfn rohs package software support ? intuitive idt hd sound graphical user interface that allows configurability and preference settings ? output path processing ? 12 band fully parametric equalizer ? compressor/limiter allows higher average volume level without resonances or damage to speakers. ? enables improved voice articulation ? constant, system-level effects tuned to optimize a particular platform can be combined with user-mode ?presets? tailored for specific acoustical environments and applications ? system-level effects automatically disabled when external audio connections made ? input path processing ? 2 band fully parametric equalizer to allow for shaping of microphone response ? compressor/limiter allows higher average volume level ? available near-field and far-field voice capture algorithms to support conference room/lecture hall applications ? microphone beam forming, acoustic echo cancellation, and noise suppression ? idt apo wrapper ? enables multiple apos to be used with the idt driver ? dynamic stream switching ? improved multi-streaming (real time communication) user experience with less support calls ? broad 3rd party branded software including creative, dolby, dts, waves, sonic focus & srs 1 dvdd_lv sdata_out bitclk sdata_in dvdd sync sense_a portc_l portc_r vrefout_b vrefout_c vreffilt fcap2 vpos avdd1 cap2 porta_r porta_l eapd pvdd dmic_clk/gpio 1 dmic_0/gpio 2 fcap1 portd_+r portd_-r portd_-l portd_+l pvss pvdd spdif/gpio3 pc_beep portb_l portb_r cpvreg avdd2 dvddio vneg hd audio interface stereo adc0 btl digital pwm controller highpass filter stereo 5-band eq 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 btl charge-pump hp hp stereo adc1 stereo dac 0 stereo dac 1 mux digital mic interface mux mux mux dac1 dac0 dmic1 dmic0 dac1 dac0 dmic1 dmic0 dac0 dac1 dac0 dac1 mux dac0 dac1 pvss dmic_1/gpio 0 reset# www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 2 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec table of contents 1. description ................................................................................................................ .......... 9 1.1. overview ................................................................................................................. ...........................9 1.2. orderable part numbers ................................................................................................... .................9 2. detailed description ..................................................................................................... 10 2.1. port functionality ............ .............. .............. .............. .............. .............. ............ ......... ......................10 2.1.1. port characteristics ............................. ...................................................................... .........10 2.1.2. vref_out ............................................................................................................... ..............11 2.1.3. jack detect ............................................................................................................ ............11 2.1.4. spdif output ........................................................................................................... ..........12 2.2. adc multiplexers ................................... ...................................................................... ....................13 2.3. power management ...... .............. .............. .............. .............. ........... ........... ........... .......... ................13 2.4. afg d0 ................................................................................................................... .........................14 2.5. afg d1 ................................................................................................................... .........................14 2.6. afg d2 ................................................................................................................... .........................14 2.7. afg d3 ................................................................................................................... .........................15 2.7.1. afg d3cold / rtd3 ...................................................................................................... .....15 2.8. vendor specific function group po wer states d4/d5 ......... .............. .............. ........... ........... .........15 2.9. 4.12 vendor specific function group power state ?d5 kill? ............ .............. .............. ........... .........16 2.10. low-voltage hda signaling ............................................................................................... ............16 2.11. multi-channel captur e ............... .............. .............. .............. .............. .............. .............. .................16 2.12. eapd .................................................................................................................... .........................18 2.13. digital microphone support .............................................................................................. .............21 2.14. analog pc-beep .......................................................................................................... ..................25 2.15. digital pc-beep ......................................................................................................... ....................27 2.16. headphone drivers ............. .............. .............. .............. .............. ........... ........... ............ .................28 2.17. class-d btl amplifier ................................................................................................... .................28 2.18. btl amplifier high-pass filter .......................................................................................... .............28 2.18.1. filter description .................................................................................................... ..........29 2.19. eq ...................................................................................................................... ............................29 2.20. combo jack detection ................................. ................................................................... ...............29 2.21. gpio .................................................................................................................... ..........................30 2.21.1. gpio pin mapping and shared functions .........................................................................30 2.21.2. spdif/gpio selection .................................................................................................. ...30 2.21.3. digital microphone/gpio selection .................................................................................30 2.22. hd audio hda015-b support ............................................................................................... .........30 2.23. digital core voltage regulator .......................................................................................... ............31 2.24. microphone mute input ................................................................................................... ...............31 3. characteristics ............................................................................................................ ... 32 3.1. electrical specifications ......................... ....................................................................... ...................32 3.1.1. absolute maximum ratings ............................................................................................... 32 3.1.2. recommended operating conditions ................................................................................32 3.2. 92HD95 analog performance characteristics (preliminary) ......................................................................33 3.3. class-d btl amplifier performance ................. ....................................................................... ........36 3.4. capless headphone supply characteristics ........ .............. .............. ........... ........... ........... ............ ...37 3.5. ac timing specs .......................................................................................................... ...................37 3.5.1. hd audio bus timing ............................. ....................................................................... .....37 3.5.2. spdif timing ........................................................................................................... ..........38 3.5.3. digital microphone timing ........................ ...................................................................... ...38 3.5.4. gpio characteristics ............................. ...................................................................... ......38 4. functional block diagram .......................................................................................... 39 5. widget diagram ............................................................................................................. ... 40 6. port and pin configurations ..................................................................................... 41 6.1. port configurations ...................................................................................................... ....................41 6.2. pin configuration default register settings ... ........................................................................... .......42 7. widget information ........................................................................................................ 4 3 7.1. widget list .............................................................................................................. .........................44 7.2. reset key ................................................................................................................ ........................45 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 3 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.3. root (nid = 00h): vendorid ............................................................................................... .............45 7.3.1. root (nid = 00h): vendorid ............................................................................................. ..46 7.3.2. root (nid = 00h): revid ................................................................................................ ....46 7.3.3. root (nid = 00h): nodeinfo ...................... ....................................................................... ..47 7.4. afg (nid = 01h): nodeinfo .. .............. .............. .............. .............. .............. .............. .......... .............47 7.4.1. afg (nid = 01h): fgtype ................................................................................................ .48 7.4.2. afg (nid = 01h): afgcap ................................................................................................ 48 7.4.3. afg (nid = 01h): pcmcap ...............................................................................................4 9 7.4.4. afg (nid = 01h): streamcap ............................................................................................5 1 7.4.5. afg (nid = 01h): inampcap .............................................................................................5 1 7.4.6. afg (nid = 01h): pwrstatecap .........................................................................................52 7.4.7. afg (nid = 01h): gpiocnt ............................................................................................... 53 7.4.8. afg (nid = 01h): outampcap ...................... ....................................................................54 7.4.9. afg (nid = 01h): pwrstate .............................................................................................. .54 7.4.10. afg (nid = 01h): unsolresp ...................... ....................................................................55 7.4.11. afg (nid = 01h): gpio ................................................................................................. ..56 7.4.12. afg (nid = 01h): gpioen ............................................................................................... 57 7.4.13. afg (nid = 01h): gpiodir .............................................................................................. 57 7.4.14. afg (nid = 01h): gpiowakeen .....................................................................................58 7.4.15. afg (nid = 01h): gpiounsol ..........................................................................................59 7.4.16. afg (nid = 01h): gpiosti cky ............. .............. .............. .............. .............. ........... .........59 7.4.17. afg (nid = 01h): subid ................................................................................................ ..60 7.4.18. afg (nid = 01h): gpioplrty ............................................................................................ 61 7.4.19. afg (nid = 01h): gpiodrive ...........................................................................................6 2 7.4.20. afg (nid = 01h): dmic ................................................................................................. ...62 7.4.21. afg (nid = 01h): dacmode ...........................................................................................63 7.4.22. afg (nid = 01h): adcmode ...........................................................................................64 7.4.23. afg (nid = 01h): eapd ..... .............. .............. .............. .............. .............. ........... ........... .65 7.4.24. afg (nid = 01h): portuse .............................................................................................. .66 7.4.25. afg (nid = 01h): comjack .............................................................................................6 7 7.4.26. afg (nid = 01h): combojacktime .................................................................................68 7.4.27. afg (nid = 01h): vspwrstate ............. .............. .............. .............. .............. ........... .........70 7.4.28. afg (nid = 01h): anaport .............................................................................................. .70 7.4.29. afg (nid = 01h): anabeep .............................................................................................7 1 7.4.30. afg (nid = 01h): anabtl ............................................................................................... 72 7.4.31. afg (nid = 01h): anabtlstatus .....................................................................................74 7.4.32. afg (nid = 01h): anacapless .........................................................................................75 7.4.33. afg (nid = 01h): reset ................................................................................................ ...78 7.5. porta (nid = 0ah): wcap .................................................................................................. ..............79 7.5.1. porta (nid = 0ah): pincap ....................... ....................................................................... ..80 7.5.2. porta (nid = 0ah): conlst .............................................................................................. ...81 7.5.3. porta (nid = 0ah): conlstentry0 ............... .......................................................................82 7.5.4. porta (nid = 0ah): conselectctrl ............... .......................................................................8 2 7.5.5. porta (nid = 0ah): pwrstate ............................................................................................ .83 7.5.6. porta (nid = 0ah): pinwcntrl ........................................................................................... .84 7.5.7. porta (nid = 0ah): unsolresp ................... .......................................................................8 4 7.5.8. porta (nid = 0ah): chsense ............................................................................................. 85 7.5.9. porta (nid = 0ah): eapdbtll r .............. .............. .............. .............. ........... ........... .........85 7.5.10. porta (nid = 0ah): configdefault ............. .......................................................................86 7.6. portb (nid = 0bh): wcap .................................................................................................. ..............89 7.6.1. portb (nid = 0bh): pincap ....................... ....................................................................... ..90 7.6.2. portb (nid = 0bh): inampleft ........................................................................................... .91 7.6.3. portb (nid = 0bh): inampright .........................................................................................9 2 7.6.4. portb (nid = 0bh): pwrstate ............................................................................................ .92 7.6.5. portb (nid = 0bh): pinwcntrl ........................................................................................... .93 7.6.6. portb (nid = 0bh): unsolresp ................... .......................................................................9 4 7.6.7. portb (nid = 0bh): chsense ............................................................................................. 94 7.6.8. portb (nid = 0bh): eapdbtll r .............. .............. .............. .............. ........... ........... .........95 7.6.9. portb (nid = 0bh): configdefault ......................................................................................9 5 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 4 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.7. portc (nid = 0ch): wcap .................................................................................................. .............98 7.7.1. portc (nid = 0ch): pincap ......................... ..................................................................... ..99 7.7.2. portc (nid = 0ch): inampleft .........................................................................................10 0 7.7.3. portc (nid = 0ch): inampright .................. .....................................................................101 7.7.4. portc (nid = 0ch): pwrstate ...........................................................................................1 01 7.7.5. portc (nid = 0ch): pinwcntrl .........................................................................................10 2 7.7.6. portc (nid = 0ch): unsolresp ................... .....................................................................103 7.7.7. portc (nid = 0ch): chsense ...........................................................................................10 3 7.7.8. portc (nid = 0ch): eapdbtllr .............. .............. .............. .............. ........... ........... .......104 7.7.9. portc (nid = 0ch): configdefault ............... .....................................................................104 7.8. portd (nid = 0dh): wcap .................................................................................................. ...........107 7.8.1. portd (nid = 0dh): pincap ......................... ..................................................................... 108 7.8.2. portd (nid = 0dh): conlst .............................................................................................. 109 7.8.3. portd (nid = 0dh): conlstentry0 ....................................................................................110 7.8.4. portd (nid = 0dh): conselectctrl .............. .....................................................................110 7.8.5. portd (nid = 0dh): pwrstate ...........................................................................................1 11 7.8.6. portd (nid = 0dh): pinwcntrl .........................................................................................11 2 7.8.7. portd (nid = 0dh): eapdbtllr .............. .............. .............. .............. ........... ........... .......112 7.8.8. portd (nid = 0dh): esdrest ............................................................................................1 13 7.8.9. portd (nid = 0dh): configdefault ............... .....................................................................113 7.9. dmic0 (nid = 0eh): wcap .................................................................................................. ...........116 7.9.1. dmic0 (nid = 0eh): pincap .............................................................................................1 17 7.9.2. dmic0 (nid = 0eh): inampleft ........................................................................................118 7.9.3. dmic0 (nid = 0eh): inampright ......................................................................................119 7.9.4. dmic0 (nid = 0eh): pwrstate ..................... .....................................................................11 9 7.9.5. dmic0 (nid = 0eh): pinwcntrl .........................................................................................12 0 7.9.6. dmic0 (nid = 0eh): configdefault .............. .....................................................................121 7.10. dmic1 (nid = 0fh): wcap ................................................................................................. ..........123 7.10.1. dmic1 (nid = 0fh): pincap ...........................................................................................12 5 7.10.2. dmic1 (nid = 0fh): inampleft .......................................................................................126 7.10.3. dmic1 (nid = 0fh): inampright ....................................................................................127 7.10.4. dmic1 (nid = 0fh): pwrstate ........................................................................................127 7.10.5. dmic1 (nid = 0fh): pinwcntrl .......................................................................................128 7.10.6. dmic1 (nid = 0fh): configdefault .................................................................................128 7.11. dac0 (nid = 10h): wcap .................................................................................................. ..........131 7.11.1. dac0 (nid = 10h): cnvtr ............................................................................................... 132 7.11.2. dac0 (nid = 10h): outampleft ................... ..................................................................133 7.11.3. dac0 (nid = 10h): outampright ................ ..................................................................134 7.11.4. dac0 (nid = 10h): pwrstate .................... .....................................................................134 7.11.5. dac0 (nid = 10h): cnvtrid ............................................................................................1 35 7.11.6. dac0 (nid = 10h) : eapdbtllr ............ .............. .............. .............. ........... ........... .......136 7.12. dac1 (nid = 11h): wcap .................................................................................................. ..........136 7.12.1. dac1 (nid = 11h): cnvtr ............................................................................................... 138 7.12.2. dac1 (nid = 11h): outampleft ................... ..................................................................139 7.12.3. dac1 (nid = 11h): outampright ................ ..................................................................139 7.12.4. dac1 (nid = 11h): pwrstate .................... .....................................................................140 7.12.5. dac1 (nid = 11h): cnvtrid ............................................................................................1 41 7.12.6. dac1 (nid = 11h) : eapdbtllr ............ .............. .............. .............. ........... ........... .......141 7.13. adc0 (nid = 12h): wcap .................................................................................................. ..........142 7.13.1. adc0 (nid = 12h): conlst ............................................................................................14 3 7.13.2. adc0 (nid = 15h): conlstentry0 ..................................................................................144 7.13.3. adc0 (nid = 15h): cnvtr ............................................................................................... 144 7.13.4. adc0 (nid = 12h): procstate ........................................................................................145 7.13.5. adc0 (nid = 12h): pwrstate .................... .....................................................................146 7.13.6. adc0 (nid = 12h): cnvtrid ............................................................................................1 47 7.14. adc1 (nid = 13h): wcap .................................................................................................. ..........147 7.14.1. adc1 (nid = 13h): conlst ............................................................................................14 9 7.14.2. adc1 (nid = 13h): conlstentry0 ..................................................................................149 7.14.3. adc1 (nid = 13h): cnvtr ............................................................................................... 150 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 5 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.14.4. adc1 (nid = 13h): procstate ........................................................................................151 7.14.5. adc1 (nid = 13h): pwrstate .................... .....................................................................152 7.14.6. adc1 (nid = 1bh): cnvtrid ...........................................................................................15 3 7.15. adc0mux (nid = 14h): wcap ............................................................................................... ......153 7.15.1. adc0mux (nid = 14h): conlst ......................................................................................155 7.15.2. adc0mux (nid = 14h): conlstentry4 ...........................................................................155 7.15.3. adc0mux (nid = 14h): conlstentry0 ...........................................................................156 7.15.4. adc0mux (nid = 14h): outampcap .............. ...............................................................156 7.15.5. adc0mux (nid = 14h): outampleft ............ ..................................................................157 7.15.6. adc0mux (nid = 14h): outampright ......... ..................................................................157 7.15.7. adc0mux (nid = 14h): conselectctrl ......... ..................................................................158 7.15.8. adc0mux (nid = 14h): pwrs tate ..................................................................................158 7.15.9. adc0mux (nid = 14h): eapd btllr ............. .............. .............. .............. .............. .......159 7.16. adc1mux (nid = 15h): wcap ............................................................................................... ......160 7.16.1. adc1mux (nid = 15h): conlst ......................................................................................161 7.16.2. adc1mux (nid = 15h): conlstentry4 ...........................................................................162 7.16.3. adc1mux (nid = 15h): conlstentry0 ...........................................................................162 7.16.4. adc1mux (nid = 15h): outampcap .............. ...............................................................163 7.16.5. adc1mux (nid = 15h): outampleft ............ ..................................................................163 7.16.6. adc1mux (nid = 15h): outampright ......... ..................................................................164 7.16.7. adc1mux (nid = 15h): conselectctrl ......... ..................................................................164 7.16.8. adc1mux (nid = 15h): pwrs tate ..................................................................................165 7.16.9. adc1mux (nid = 15h): eapd btllr ............. .............. .............. .............. .............. .......166 7.17. portmux (nid = 16h): wcap .. .............. .............. .............. .............. .............. .............. ......... .........166 7.17.1. portmux (nid = 16h): conlst .........................................................................................16 8 7.17.2. portmux (nid = 16h): conlstentry0 ......... .....................................................................168 7.17.3. portmux (nid = 16h): conselectctrl ......... .....................................................................169 7.17.4. portmux (nid = 16h): pwrstate ................ .....................................................................169 7.18. spdifout0 (nid = 17h): wcap ............................................................................................. ......170 7.18.1. spdifout0 (nid = 17h): pcmcap ................................................................................171 7.18.2. spdifout0 (nid = 17h): streamcap .............................................................................173 7.18.3. spdifout0 (nid = 17h): outampcap ...........................................................................173 7.18.4. spdifout0 (nid = 17h): cnvtr ......................................................................................174 7.18.5. spdifout0 (nid = 17h): outampleft ............................................................................175 7.18.6. spdifout0 (nid = 17h): outampright .........................................................................176 7.18.7. spdifout0 (nid = 1dh): pwrstate .............. ..................................................................176 7.18.8. spdifout0 (nid = 17h): cnvtrid ...................................................................................177 7.18.9. spdifout0 (nid = 17h): digcnvtr .................................................................................178 7.19. dig0pin (nid = 18h): wcap ............................................................................................... ..........179 7.19.1. dig0pin (nid = 18h): pincap .................... .....................................................................18 0 7.19.2. dig0pin (nid = 18h): conlst .........................................................................................18 1 7.19.3. dig0pin (nid = 18h): conlstentry0 ...............................................................................182 7.19.4. dig0pin (nid = 18h): pwrsta te ......................................................................................182 7.19.5. dig0pin (nid = 18h): pinwcntrl .....................................................................................183 7.19.6. dig0pin (nid = 18h): unso lresp ..................................................................................184 7.19.7. dig0pin (nid = 18h): chsense ......................................................................................184 7.19.8. dig0pin (nid = 18h): configdefault .......... .....................................................................185 7.20. digbeep (nid = 19h): wcap .......................... ..................................................................... ........187 7.20.1. digbeep (nid = 19h): outampcap .............. ..................................................................188 7.20.2. digbeep (nid = 19h): outa mpleft ................................................................................189 7.20.3. digbeep (nid = 19h): pwrsta te .....................................................................................190 7.20.4. digbeep (nid = 19h): gen .............................................................................................1 90 7.20.5. digbeep (nid = 19h): gain ..................... .......................................................................1 91 7.21. advancedfunctions (nid = 1ah): wcap ..................................................................................... 191 7.21.1. advancedfunctions (nid = 1ah): cntrl0 ........................................................................193 7.21.2. advancedfunctions (nid = 1ah): cntrl1 ........................................................................193 7.21.3. advancedfunctions (nid = 1ah): cntrl2 ........................................................................194 7.21.4. advancedfunctions (nid = 1ah): cntrl3 ........................................................................194 8. pinout and packaging .................................................................................................. 208 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 6 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 8.0.1. 40-qfn pin table ....................................................................................................... .....209 8.0.2. 40-qfn package outline a nd package dimensions .............. ............ ........... ........... .......210 8.1. standard reflow profile data ............................................................................................. ...........211 9. disclaimer ................................................................................................................. ........ 212 10. document revision history ..................................................................................... 212 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt? confidential 7 v 0.91 06/12 ?2009 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec list of figures figure 1. multi-channel capture ... .............. .............. .............. .............. .............. ........... ........... .......................17 figure 2. multi-channel timing diagr am ............. .............. .............. .............. ........... ........... ........... ..................17 figure 3. hp eapd example to be replaced by single pin for internal amp ............. .............. .............. .........21 figure 4. eapd implementation ................................................................................................. ....................21 figure 5. single digital microphone (data is ported to both left and right channels .. .............. .............. .........23 figure 6. stereo digital microphone configuration ............................................................................. ...........24 figure 7. quad digital microphone configuration ........ ....................................................................... ...........25 figure 8. analog pc beep active ........................ ....................................................................... ...................26 figure 9. analog pc beep flow chart .................. ......................................................................... .................27 figure 10. combo jack ......................................................................................................... .........................29 figure 11. hd audio bus timing ................................................................................................ ....................37 figure 12. functional block diagram ........................................................................................... ..................39 figure 13. widget diagram ..................................................................................................... .......................40 figure 14. port configurations ................................................................................................ .......................41 figure 15. 40-qfn pin assignment .............................................................................................. ...............208 figure 16. 40-qfn package diagram ....................... ...................................................................... .............210 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt? confidential 8 v 0.91 06/12 ?2009 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec list of tables table 1. port functionality ................................................................................................... ..........................10 table 2. analog output port behavior ................. ......................................................................... .................11 table 3. jack detect .......................................................................................................... ............................12 table 4. spdif out 0 behavior .......................... ....................................................................... ...................12 table 5. power management ........... .............. .............. .............. .............. ........... ............ ........... ....................13 table 6. example channel mapping ........................ ...................................................................... .................17 table 8. eapd pin mode select .......................... ....................................................................... ...................19 table 9. control bit descriptions for btl amplifier an d headphone amplifier enable configurations .............19 table 10. btl amp enable configurat ion ........................................................................................ ..............19 table 11. headphone amp enable configuration .............. .............. .............. .............. .............. ............ ........19 table 12. eapd analog pc_beep behav ior ............. .............. .............. .............. ............ ........... .......... ..........20 table 13. eapd behavior ............. .............. .............. .............. .............. ............ ........... ........... .......................20 table 14. valid digital mic configurations ........... ......................................................................... .................22 table 15. dmic_clk and dmic_0,1 operation during powe r states ..........................................................22 table 16. electrical specification: maximum ratings ........................................................................... .........32 table 17. recommended operating conditions .................................................................................... ........32 table 18. 92HD95 analog performance characteristics ... ........................................................................ ....33 table 19. class-d btl amplifier performance ................................................................................... ...........36 table 20. capless headphone supply ........................ .................................................................... ..............37 table 21. hd audio bus timing ................................................................................................. ....................37 table 22. spdif timing ........................................................................................................ .........................38 table 23. digital mic timing ............................ ...................................................................... ..........................38 table 24. gpio characteristics ................................................................................................ .....................38 table 25. pin configuration default settings .......... ........................................................................ ...............42 table 26. command format for verb with 4-bit identifier ............. .............. ........... ........... ............ .......... .......43 table 27. command format for verb with 12-bit identifi er ...................................................................... ......43 table 28. solicited response format ........................................................................................... .................43 table 29. unsolicited response format ......................................................................................... ...............43 table 30. widget list ............... .............. .............. .............. .............. .............. ........... ......... ............................44 table 31. 40qfn pin description ............................................................................................... .................209 table 32. standard reflow profile .............. .............. .............. .............. .............. ............ ........... ..................211 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 9 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 1. description 1.1. overview the 92HD95 audio codec provides stereo 24- bit, fu ll duplex resolution supporting sample rates up to 192khz by the dac and adc. spdif output supp orts sample rates of 192khz, 96khz, 88.2khz, 48khz, and 44.1khz. additional sample ra tes are supported by the driver software. an integrated btl stereo amplifie r is ideal for driving 4ohm or 8ohm integrated speakers in mobile and ultra-mobile computers. for desktop computer s or mobile computers using only one speaker, the btl output stage may be configured to support a single mono speaker. the 92HD95 includes an integrated class-g true capless stereo headphone amplifier with charge pump and ldo. the 92HD95 supports a wide range of desktop and laptop configurations. the spdif output inter- faces provide connectivity to cons umer electronic equipment or to a home entertainment system. all inputs can be programmed with 0-30 db gain in 10 db steps allowing for line or microphone use of any input. port presence detect capabilitie s allow the codec to detect when audio devices are connected to the codec. the fully parametric internal eq can be initiated upon headphone jack insertion and removal for protection of notebook speakers. the 92HD95 also supports the intel runtime d3 (rtd3) low power state for always on, always connected. the 92HD95 audio codec operates with a 3.3v di gital supply and a 3.3v analog supply. it allows for 1.5v and 3.3v hda signaling; the correct signa lling level is selected dy namically based on the power supply voltage on the dvdd-io pin. the 92HD95 audio codec is offered in a 40-pin qfn environmental (rohs) package. 1.2. orderable part numbers yy = silicon stepping/revision, contact sales for current data. add an ?8? to the end for tape and reel delivery. 92HD95b2x3ndgxyyx 4ch, 40qfn, switchable 1.5v or 3.3v hda signaling, 3.3v avdd www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 10 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2. detailed description 2.1. port functionality multi-function (input/outpu t) ports allow for the highest possible flexibility and supporting a wide vari- ety of consumer desktop and mobile system use models. ? port a supports ? cap-less headphone out ? cap-less line out ? port b supports ? line input ? mic with 0/10/20/30 db boost and vref_out ? port c supports ? line input ? mic with 0/10/20/30 db boost and vref_out ? port d supports ? btl stereo output ? btl (l+/l-) mono out 2.1.1. port characteristics port a is designed to drive 32 ohm (nominal) headphones or a 10k (nominal) load. input ports are 50k (nominal) at the pin. dac full scale outputs and intended full scale input levels are 1v rms at 3.3v. line output ports and headphone output ports on the codec may be configured for +3dbv full scale output levels (0.707vrms) by using a vendor specific verb. unused ports should be left unconnected. when updating existing designs to use the codec, ensure that there are no conflicts between the output ports on the codec and existing circuitry. pins 40-qfn port input output headphone btl mic bias (vref pin) input boost amp 22/23 a yes yes 17/18 b yes yes yes 14/15 c yes yes yes 32/33/36/37 d yes yes 3 (clk=2) e (dmic0) yes na yes 4 (clk=2) f (dmic1) yes na yes 40 spdif_out yes table 1. port functionality www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 11 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2.1.2. vref_out ports b & c support vref_out pins for biasing el ectret cartridge microphones. settings of 80% avdd, 50% avdd, gnd, and hi-z are supported. a ttempting to program a pin widget control with a reserved or unsupported value will cause the asso ciated vref_out pin to assume a hi-z state and the pin widget control vref_en field will retu rn a value of ?000 ? (hi-z) when read. 2.1.3. jack detect plugs inserted to a jack on ports a, b, c & spdifout are detected using sense_a. per hda015-b, the detection circuit operates when the codec is in d0 - d3 and can also operate if both the codec and controller are in d3 (no bus clock.) jack dete ction requires that all supplies afg power state input enable output enable used as output for dac/mixer used as output for analog pc_beep used as input for adc, mixer port behavior d0-d2 1 1 don't care don't care yes not allowed. port is active as input. no not allowed. inactive (power down) - port keeps output coupling caps charged if port uses caps. 1 0 na na yes active - port enabled as input 1 0 na na no inactive (power down) - port keeps output coupling caps charged if port uses caps. 01 currently used by dac, mixer, beep, or is traditional line or headphone output na active - port enabled as output 01 not currently used by dac, mixer, beep and is capless hp/btl port inactive (power down) 0 0 na na na inactive (power down) - port keeps output coupling caps charged if port uses caps. d3 1 1 na na don't care not allowed. inactive (power down) - port keeps output coupling caps charged if port uses caps. 1 0 na na don't care inactive (power down) - port keeps output coupling caps charged if port uses caps. 01 currently used by dac, mixer, beep, or is traditional line or headphone output don't care low power state. if enabled, beep will output from the port 01 not currently used by dac, mixer, beep and is capless hp/btl port don't care inactive (power down) 0 0 na na don't care inactive (power down) - port keeps output coupling caps charged if port uses caps. d3cold - - inactive (lower power) - port keeps output coupling caps charged if port uses caps. d4 - - inactive (lower power) - port keeps output coupling caps charged if port uses caps. d5 - - off - charge on coupling caps (if used) will not be maintained. table 2. analog output port behavior www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 12 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec (analog and digital) are active and stable. when avdd is not present, the value reported in the pin widget is invalid. when the hd audio bus is in a low power state (r eset asserted and cloc k stopped) the codec will generate a power state change request when a change in port connectivity is sensed and then generate an unsolicited response after the hd audio link has been brought out of a low power state and the device has been enum erated. per hda015-b, this will take less than 10ms. the following table summarizes the proper resistor tolerances for different analog supply voltages. see reference design for more information on jack detect implementation. 2.1.4. spdif output the spdif output can operate at 44.1khz, 48khz, 88.2khz, 96khz and 192khz as defined in the intel high definition audio specific ation with resolutions up to 24 bi ts. this insures compatibility with all consumer audio gear and allows for convenient integration into home theater systems and media center pcs. per the hda015-b, the spdif output s support the ability to provide clocking information even when no stream is selected for the converter, or when in a low power state. also, the spdif output port supports port presence detect. spdif output is outlined in table below. avdd nominal voltage (+/- 5%) resistor tolerance pull-up resistor tolerance sense_a 3.3v 1% 1% resistor sense_a 39.2k port a 20.0k port b 10.0k port c 5.11k spdifout 2.49k pull-up to avdd table 3. jack detect afg power state reset# output enable converter dig enable stream id keep alive enable pin behavior d0-d3 asserted (low) - - - - hi-z (internal pull-down enabled) immediately after power on, otherwise the prev ious state is retained. d0 de-asserted (high) disabled - - - hi-z (internal pull-down enabled) de-asserted (high) enabled disabled - - active - pin drives 0 (internal pull-down na) de-asserted (high) enabled enabled 0 - active - pin drives spdif-format, but data is zeroes (internal pull-down na) de-asserted (high) enabled enabled 1-15 - active - pin drives spdifout0 data (internal pull-down na) table 4. spdif out 0 behavior www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 13 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2.2. adc multiplexers the codec implements 2 adc input multiplexers. these multiplexers incor porate the adc record gain function:(-16 to +30db gain in 1db steps) as an output amp and allow a preselection of one of below possible inputs: ? port mux (selects between port b and port c) ?dmic 0 ?dmic 1 ?dac0 ?dac1 2.3. power management the hd audio specification defines power states, power state widgets, and power state verbs. power management is implemented at several leve ls. the audio function group (afg) , all con- verter widgets, and all pin complexes support the power state verb f05/705. converter widgets are active in d0 and inactive in d1-d3. the following table describes what function ality is active in each power state. d1-d2 de-asserted (high) disabled - - - hi-z (internal pull-down enabled) de-asserted (high) enabled - - 0 active - pin drives 0 (internal pull-down na) enabled - 1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3 de-asserted (high) - - - 0 hi-z (internal pull-down enabled) disabled - - 1 hi-z (internal pull-down enabled) enabled enabled - 1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3cold / rtd3 - - - - - hi-z (internal pull-down enabled) d4 - - - - - hi-z (port off) d5 - - - - - hi-z (port off) function d0 d1 1 d2 d3 d3cold / rtd3 vendor specific d4 vendor specificd5 spdif output on on on (idle) on (idle) 5 off off off digital microphone inputs on off off off off off off dac on off off off off off off adc on off off off off off off adc volume control on off off off off off off ref adc on off off off off off off analog clocks on off off off off off off gpio pins on on on on 5 on on off table 5. power management afg power state reset# output enable converter dig enable stream id keep alive enable pin behavior table 4. spdif out 0 behavior www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 14 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec the d3-default state is available for hd audio compliance. the programmable values, exposed via vendor-specific settings, are under idt device driver control for further power reduction. the analog mixer, line and headphone amps, port presence detect, and internal references may be disabled using vendor specific verbs. use of t hese vendor specific verbs will cause pops. the default power state for the audio function group after reset is d3. 2.4. afg d0 the afg d0 state is the active state for the device. all functions are active if their power state (if they support power management at their node level) has been set to d0. 2.5. afg d1 d1 is a lower power mode where all converter wid gets are disabled. analog mixer and port functions are active. the part will resume from thed1 to thed0 state within 1 ms. 2.6. afg d2 the d2 state further reduces power by disabling t he mixer and port function s. the port amplifiers and internal references remain ac tive to keep port coupling caps charged and the system ready for a quick resume to either th e d1 or d0 state. the part will resume from the d2 stat e to the d0 state within 2ms. vrefout pins on on off off off off off input boost on on off off off off off analog pc_beep on on on on off off off digital pc_beep on on on on 5 off off off capless lo/hp amps on on on low drive 2 low drive 2 low drive 2 off btl amp on on on low drive 2 off off off vag amp on on on low drive 3 low drive low drive off port sense ononon on 4 off off off reference bias generator on on on on on on off reference bandgap core on on on on on on off hd audio-link on on on on 5 limited off off 1. no dac or adc streams are active. analog mixing and loop thru are supported . 2. vag is kept active when ports are disabled or in d3/d3c old/d4. pc_beep is supported in d3 but may be attenuated and distorted depending on load impedance. hendrix and kaveri will shut down the capless headphone amplifiers and btl amplifier in d3 and below. in d3, the codec will turn on the btl and capless amplifiers if activity is detected on the pc_beep input and analog pc_beep is enabled. 3. vag is always ramped up and down gradually, except in the case of a sudden power removal. vag is active in d2/d3 but in a low power state. 4. both avdd and dvdd must be avai lable for port sense to operate. 5. not active if bitclk is not running (controller in d3), but can signal power state change request (pme) function d0 d1 1 d2 d3 d3cold / rtd3 vendor specific d4 vendor specificd5 table 5. power management www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 15 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2.7. afg d3 the d3-default state is available for hd audio compliance. all conver ters are shut down. port ampli- fiers and references are active but in a low power state to prevent pops. resume times may be lon- ger than those from d2, but still less than 10ms to meet intel low power goals. the default power state for the audio function group after power is applied is d3. while in afg d3, the hd audio controller may be in a d0 state (hd audio bus active) or in a d3 state (hd audio bus held in reset with no bit_clk, sdata_out, or sync activity.) the expected behav- ior is as follows (see the hda015- b section for more information): 2.7.1. afg d3cold / rtd3 the d3cold/rtd3 power state is the lowest power state available that does not use vendor specific verbs. while in d3cold/rtd3, th e codec will still respond to bus requests to reve rt to a higher power state (double afg reset, link reset). howeve r, audio processing, port presence detect, and other functions are disabled. per the hd audio bus hda015-b, the d3cold state is intended to be used just prior to removing power to the co dec. typically, power will be removed within 200ms. however, the codec may exit from the d3cold/rtd3 state by generating 2, back-to-back, afg reset events. resume time from d3co ld/rtd3 is less than 200ms. the codec also supports intel?s runtime d3 (rtd3) state for always on, always connected support. 2.8. vendor specific functi on group power states d4/d5 the codec introduces vendor specific power states. a vendor defined verb is added to the audio function group that combines multiple vendor spec ific power control bits into logical power states for use by the audio driver. the 2 states defined of fer lower power than the 5 existing states defined in the hd audio specification and hda015-b. the vendor specific d4 state provides lower digital power consumption relative to d3co ld by disabling hd audio link responses. vendor specific d5 fur- ther reduces power consumption on the digital supply by turning off gpio drivers, and reduces ana- log power consumption by turning off all an alog circuitry except for reset circuits. states d4/d5 are not entered until d3cold has been requested so are actually d3cold options rather than true, independent, power states. software can pr e-program the d4 or d5 state as a re-definition of how the part will behav e when the d3cold power state is req uested or software may enter d3cold, then set the d4 or d5 before performing the po wer state get command. the preferred method is to request d3cold, then select d4 or d5 as desired.this will reduce th e severity of pops encountered when entering d4 or d5. both power states require a link re set or removal of dvdd to exit. the codec may pop when using these verbs and transi tion times to an active state (d1 or d0 for example) may take several seconds. function hda bus active hda bus stopped port presence detect state change unsolicited re sponse wake event followed by an unsolicited response gpio state change unsolicited response wake event followed by an unsolicited response www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 16 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2.9. 4.12 vendor specific function group power state ?d5 kill? vendor specific ?d5 kill? places t he device in a low power, non respon sive, state that is intended to disable the codec when, for security reasons, it is desired that no audio playback or recording take place. state ?d5 kill? is not entered until d3cold has be en requested. software pr e-programs both the d4 and d5 state request bits (d4 and d5 = 1) then request d3cold. after responding to the function group power state get verb (need ed to enter d3cold), the codec will no longer respond to any link activity. the only way to exit this state is to re move power (power on rese t will set the power state to d3.) ?d5 kill? is identical to vendor specific d5 with th e exception that the codec will only exit this state when power is removed. 2.10. low-voltage hda signaling the codec is compatible with eit her 1.5v or 3.3v hda bus signaling; in the 48-qfn package the voltage selection is done dynamically based on the input voltage of dvdd_io. dvdd_io is currently not a logic configuration pin, but rather provides the digital power supply to be used for the hda bus signals. when in 1.5v mode, the codec can correctly decode bitclk, sync, reset# and sdo as they operate at 1.5v; addition ally it will drive sdi and sdo at 1.5v . none of the gpios are affected, as they always function at their nominal voltage (dvdd or avdd). 2.11. multi-channel capture the capability to assign multiple adc converters to the same str eam is supported to meet the microphone array requirements of vista and future operating systems. single converter streams are still supported this is done by assi gning unique non zero stream ids to each converter. all capture devices (adcs 0 and 1) may be used to create a multi-channel input stream. there are no restric- tions regarding digital microphones. the adc converters can be associated with a single stream as long the sample rate and the bits per sample are the same. the assignment of converter to channel is done using the ?cnvtrid? widget and is restricted to even values. the adc conver ters will always put out a stereo sample and there- fore require 2 channels per converter. the stream will not be generated unle ss all entries for the targeted converters are set identically, and the total number of assigned converter channels ma tches the value in the nmbrchan field. these are listed the ?multi-converter stream critical entries.? table. an example of a 4 channel steam with adc0 supplying channels 0&1 and adc1 supplying chan- nels 2 & 3 is shown below. a 4 channel stream can be created by assigning the same non-zero stream id ?strm= n? to both adc0 and adc1. the sample rates must be se t the same and the num- ber of channels must be set to 4 channels ?nmbrchan = 0011?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 17 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 1. multi-channel capture the following figure describes the bus waveform for a 24-bit, 48khz capture stream with id set to 1. figure 2. multi-channel timing diagram adc1 cnvtrid (nid = 0x08) [3:0] ch = 2 adc0 cnvtrid (nid = 0x07) [3:0] ch=0 table 6. example channel mapping adc[1:0] cnvtr bit number sub field name description [15] strmtype stream type (type): 0: pcm 1: non-pcm (not supported) [14] frmtsmplrate sample base rate 0= 48khz 1=44.1khz [13:11] smplratemultp sample base rate multiple 000=48khz/44.1khz or less 001= x2 010= x3 (not supported) 011= x4 192khz only, 176.4 not supported 100-111= reserved table 7: mult-channel stream id data length adc0 left channel adc0 right channel adc1 left channel adc1 right channel stream id data length adc1 left channel adc1 right channel adc0 left channel adc0 right channel adc0.cnvrtid.channel = 0 adc1.cnvrtid.channel = 2 adc0.cnvrtid.channel = 2 adc1.cnvrtid.channel = 0 0 0 0 sdi bitclk 1 0 0 1 1 0 0 stream id data length stream tag adc0 l23 adc0 l0 adc0 r23 adc0 r0 adc1 l23 adc1 l0 adc1 r23 adc1 r0 left left right right adc0 adc1 data block www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 18 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 2.12. eapd the eapd pin is a dedicated, bi-d irectional control pin. although named external amplifier power down (eapd) by the hd audio specif ication, this pin operates as an external amplifier power up sig- nal. the eapd value is re flected on the eapd pin; a 1 causes the external amplifier to power up (equivalent to d0), and a 0 causes it to power down (equivalent to d3.) when the eapd value = 1, the eapd pin must be placed in a state appropriate to the current po wer state of the associated pin widget even though the eapd value (in the register) may remain 1. the default state of this pin is 0 (driving low.) the pin defaults to an open-drain configuration (an external pull-up is recommended.) per the hd audio specification and hda015-b, multip le ports may control eapd. the eapd pin assumes the highest power state of all the eapd bits in all of the pin complexes. the default value of eapd is 1 (powered on), but the fg power state will override and the pin will be low. a port will request external amp power up when its power stat e is active (fg and pin widget power state is d1 or d0) or (analog pc_beep is enabled and port is enabled as an output) a nd the port?s eapd bit is set to 1. the state of the eapd pi n (unless configured as an input or held low by an external circuit when configured as an open dr ain output) will be the logical or of the external amp power up requests from all ports. by default, the eapd pin al so functions as t he mute#/shutdown# input for the internal btl amplifier. in this mode, a low value at the pin (either due to internal eapd being 0, or to an external entity forc- [10:8] smplratediv sample base rate divisor 000= divide by 1 001= divide by 2 (not supported) 010= divide by 3 (not supported) 011= divide by 4 (not supported) 100= divide by 5 (not supported) 101= divide by 6 (not supported) 110= divide by 7 (not supported) 111= divide by 8 (not supported) [6:4] bitspersmpl bits per sample 000= 8 bits (not supported) 001= 16 bits 010= 20 bits 011= 24 bits 100-111= reserved [3:0] nmbrchan number of channels number of channels for this stream in each ?sample block? of the ?packets? in each ?frame? on the link. 0000=1 channel (not supported) 0001 = 2 channels ? 1111= 16 channels. [7:4] strm software-programmable integer representing link stream id used by the converter widget. by conven- tion stream 0 is reserved as unused. [3:0] ch integer representing lowest channel used by con- verter. 0 and 2 are valid entries if assigned to the same stream, one adc must be assigned a value of 0 and the other adc assigned a value of 2. table 7: mult-channel www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 19 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec ing the pin low) will cause the intern al btl amplifier to mute or en ter a low power state depending on the amplifier configur ation. (see below) vendor specific verbs are available to configure this pin. these verbs retain their values across link and single function group resets but are set to their default values by a power on reset: mode1 mode0 eapd pin function description 0 0 open drain i/o value at pin is wired-and of eapd bit and external signal.(default) 0 1 cmos output value of eapd bit in pin widget is forced at pin 1 0 cmos input external signal controls internal amps. eapd bit in pin widget ignored 1 1 cmos input external signal controls internal amps. eapd bit in pin widget ignored table 8. eapd pin mode select control flag description eapd pin mode 1:0 defines if eapd pin is used as in put, output, or bi-direc tional port (open drain) btl/hp sd 0 = amp cont rolled by eapd pin only (default) / 1 = amp controlled by power st ate (pin and fg) only btl/hp sd mode 0 = amp will mute when disabled. (default for za and zb only) / 1 = amp will shut down (enter a low power state) when disabled (default for ya forward) btl/hp sd inv 0 = amp will power down (or mute) when eapd pin is low (default) / 1 = amp will power down (or mute) when eapd pin is high. table 9. control bit descriptions for btl amplifier and headphone amplifier enable configurations btl sd btl sd mode btl sd inv eapd pin state btl amp state 0 0 0 0 amplifier is mute 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state (default 1 ) 1. eapd bit is set to one by default but th e eapd state is 0 after powe r-on reset because t he function group is not in d0. the state after a single or double function group reset will be compliant with hda015-b. 0 1 0 1 amplifier is active 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/function group power state and will mute when disabled 1 1 na na amplifier follows pin/function group pow er state and will enter a low power state when disabled table 10. btl amp enable configuration hp sd hp sd mode hp sd inv eapd pin state headphone amp state 0 0 0 0 amplifier is mute 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state (default 1 ) 0 1 0 1 amplifier is active table 11. headphone amp enable configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 20 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/function group power state and will mute when disabled 1 1 na na amplifier follows pin/function group pow er state and will enter a low power state when disabled 1. eapd bit is set to one by default but the eapd state is 0 af ter power-on reset because the function group is not in d0. the state after a single or double function group reset will be compliant with hda015-b. analog beep enabled eapd pin value 1 1. when pin is enabled as open drain or cmos output. description 0 forced to low when in d2 or d3 follows description in hd audio spec. external amplifier is shut down when pin or function group power state is d2 or d3 independent of value in eapd bit. 1 forced low in d2 or d3 unless port is enabled as output power state is ignored if port is enabled as output and port eapd=1 to allow pc_beep support in d2 and d3 table 12. eapd analog pc_beep behavior afg power state reset# analog pc_beep port power state pin behavior d0-d3 asserted (low) - - active low immediately after po wer on, otherwise the previous state is retained across fg and link reset events d0 de-asserted (high) - - active - pin reflects eapd bit unless held low by external source. d1 de-asserted (high) - d0-d1 active - pin reflects eapd bit unless held low by external source. d2 de-asserted (high) disabled d0-d2 pin forced low to disable external amp d2 de-asserted (high) enabled d0-d2 active - eapd pin high if any port eapd bit =1 and that port also enabled as output. d3 de-asserted (high) disabled d0-d3 pin forced low to disable external amp d3 de-asserted (high) enabled d0-d3 active - eapd pin high if any port eapd bit=1 and that port also enabled as output. d3cold/ rtd3 de-asserted (high) - - pin forced low to disable external amp d4 de-asserted (high) - - pin forced low to disable external amp d5 de-asserted (high) - - pin hi-z (off) table 13. eapd behavior hp sd hp sd mode hp sd inv eapd pin state headphone amp state table 11. headphone amp enable configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 21 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 3. hp eapd example to be replaced by single pin for internal amp figure 4. eapd implementation 2.13. digital microphone support the digital microphone interface permits connection of a digital microphone(s) to the codec via the dmic0, dmic1, and dmic_clk 3-pi n interface. the dmic0 and dmic1 signals are inputs that carry individual channels of digital microphone data to the adc. in the event that a single microphone is used, the data is ported to both adc channels. this mode is selected using a vendor specific verb and the left time slot is copied to the adc left and right inputs. the dmic_clk output is controllable from 4.70 4mhz, 3.528mhz, 2.352mhz, 1.176mhz and is syn- chronous to the internal master cloc k. the default frequency is 2.352mhz. the two dmic data inputs are reported as two st ereo input pin widgets that incorporate a boost amplifier. the pin widgets are shown connected to the adcs through the same multiplexors as the mute + up/down buttons kbc codec spkr amp scan codes os a_sd a_eapd spkr_en# gpio_1 sync from audio gui to kbc sync from kbc to os (mute led on same board) hp audio control block diagram smu mute other external power amp sd# internal btl amp eapd pin control sd/mute codec vdd eapd sd/mute internal headphone amp www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 22 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec analog ports. although the internal implementation is different between the analog ports and the dig- ital microphones, the functionality is the same. in most cases, the default va lues for the dmic clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. to conserve power, the analog portion of the ad c will be turned off if the d-mic input is selected. when switching from the digital microphone to an analog input to the adc, the analog portion of the adc will be brought back to a full power state and allowed to stabilize before switching from the dig- ital microphone to the analog input. this should take less than 10ms. dmic pin widgets support port presence detect directly using sense-b input. the codec supports the following digital microphone configurations: digital mics data sample adc conn. notes 0 n/a n/a no digital microphones 1 single edge 0, or 1 available on either dmic_0 or dmic_1 when using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone fo r ?left? and select mono operation using the vendor specific verb. ?left? d-mic data is used for adc left and right channels. 2 double edge on either dmic_0 or 1 0, or 1 available on either dmic_0 or dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge (multiplexed output) capability. 3 double edge on one dmic pin and single edge on the second dmic pin. 0, or 1 requires both dmic_0 and dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge (multiplexed output) capability. tw o adc units are required to support this configuration 4 double edge 0, or 1 connected to dmic_0 and dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge capability. two adc units are required to support this configuration table 14. valid digital mic configurations power state dmic widget enabled? dmic_clk output dmic_0,1 notes d0 yes clock capable input capable dmic_clk output is enabled when either dmic_0 or dmic_1 input widget is enabled. otherwise, the dmic_clk remains low d1-d3 yes clock disabled input disabled dmic _clk is high-z with weak pull-down d0-d3 no clock disabled input disabled dmic _clk is high-z with weak pull-down d4 - clock disabled input disabled dmic_c lk is high-z with weak pull-down d5 - clock disabled input disabled dmic_c lk is high-z with weak pull-down table 15. dmic_clk and dmic_0,1 operation during power states www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 23 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 5. single digital microphone (data is ported to both left and right channels dmic_0 or dmic_1 dmic_clk right channel left channel valid data valid data valid data dmic_0 or dmic_1 dmic_clk single line in pin on-chip multiplexer pin digital microphone on-chip off-chip mux stereo channels output stereo adc0 or 1 pcm dmic_0 or dmic_1 dmic_clk left & right channel valid data valid data valid data valid data single ?left? microphone, dmic input set to mono input mode. single microphone not supporting multiplexed output. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 24 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 6. stereo digital microphone configuration note: some digital microphone implementations support data on either edge, therefore, the external mux may not be required. dmic_0 or dmic_1 dmic_clk right channel left channel valid data r valid data l valid data r valid data l valid data r digital microphones dmic_clk mux stereo channels output pin pin external multiplexer on-chip multiplexer on-chip off-chip stereo adc0 or 1 pcm mux dmic_0 or dmic_1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 25 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 7. quad digital microphone configuration note: some digital microphone implementations support data on either edge, in this case the external multiplexe r is not required. 2.14. analog pc-beep the codec supports automatic routin g of the pc_beep pin to port a and port d outputs when the hd-link is in reset. when the link is active (not held in reset) analog pc-beep may be enabled manually. analog pc_beep is mixed at the por t and only ports enabled as outputs will pass pc_beep. dmic_1 dmic_clk dmic_0 right channel left channel valid data r1 valid data l1 valid data r1 valid data l1 valid data r1 valid data r0 valid data l0 valid data r0 valid data l0 valid data r0 right channel left channel mux stereo channels output for dmic_0 l&r on-chip multiplexer stereo adc0 pcm mux stereo channels output for dmic_1 l&r on-chip multiplexer stereo adc1 pcm digital microphones dmic_clk pin pin external multiplexer mux dmic_0 on-chip off-chip digital microphones pin external multiplexer mux dmic_1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 26 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec beep activity monitoring is provided when the an alog beep path is enabled and the codec or ampli- fier is in a low power state (d3). the analog pc beep input is sampled for 500us every 1ms. if the beep input is high or low (>200mvpp) for at least 37% of that time, it is considered active. if it is active for less than 7.5% of that time, it is possibly inactive. if no activi ty is detected for 64ms (128ms, 256ms and 512ms also selectable for the idle threshold), then beep is considered inactive. figure 8. analog pc beep active phase 1: analog beep auto-routing phase in the period af ter application of dvdd, before the first ris- ing edge of link reset. once analog pcbeep is detecte d(beep_presence=1) after 64ms de lays (after por (power on reset)), the amplifier will be turned on(port_pwd= 0, port_output_en=1, there is a timing between these two signals) and analog _beep_en=1. if beep_presence=0 fo r longer than the threshold time, the amplifiers will be turned off to save power and preven t unwanted system noise from being heard. phase 2: when not in phase 1 a. if analog beep function is disabled by driver. analog beep auto- detect will also be disabled. b. if analog beep function is enabled by driver. once analog pcbeep is detected(beep_pres ence=1), analog pc_beep will be enabled if in d0-d2, enabled simply means muting or un-muting beep to avoid hearing system noise on the beep input pin but it is acceptable to turn off port amplifiers if not currently used by dacs, mixer, or beep to save power. if in d3, enabled means that the necessary amplifiers are turned on so that the beep signal may be heard on all ports configured as outputs (see analog pc-beep description section above) all needed amplifiers ar e enabled until beep_presence=0 for longer than the idle threshold a flow chart of analog pc beep is below. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 27 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec figure 9. analog pc beep flow chart 2.15. digital pc-beep this block uses an 8-bit divider value to generate the pc beep from the 48khz hd audio sync pulse. the digital pc_beep block generates the beep tone on all pin complexes that are currently configured as outputs. the hd audio spec states that the beep tone frequency = (48khz hd audio por wait 64ms activity on pin? link reset active? turn on amplifiers / enable beep path activity on pin? no analog pc_beep enabled? yes yes yes yes activity on pin? inactivity over threshold? disable beep path / turn off amplifiers no yes no no no idle no no www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 28 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarithmic scale). other audio sources are disabled when digital pc_beep is active. it should be noted that digital pc be ep is disabled if the divider = 00h. pc-beep may be attenuated and distorted when the codec is in d3 depending on the load imped- ance seen by the output amplifier since all port s are in a low power state while in d3. load imped- ances of 10k or larger can supp ort full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. digital pc_beep requires a clock to operate and the codec will prevent the system from stopping the bus clock wh ile in d3 by setting the clock_stop_ok bit to 0 to indicate that the part requires a clock. 2.16. headphone drivers the codec implements class-g cap-less headphone outputs. the microsoft windows logo program allows up to the equivalent of 100ohms in series . however, an output level of +3dbv at the pin is required to support 300mv at the jack with a 32 ohm load and 1v with a 320 ohm load. microsoft allows device and system manufact ures to limit output voltages to address eu safety requirements. (wlp 3.09 - please refer to the latest windows logo program requirements from microsoft.) the codec does not support power limiting. the cap-less headphone drivers are supplied with +/-2.5v derived from avdd. therefore, it is possi- ble to run the headphone supply from 3.3v to 5v and maintain ~60mw peak output power into 32 ohm headphones. 2.17. class-d btl amplifier an integrated class-d stereo btl amplifier is pr ovided to directly drive 4 ohm speakers (2w @ 4.75v) or 8 ohm speakers (1w @ 4.75v). no external filter is needed for cable runs of 18? or less. an internal dc blocking filter prevents distorti on when the audio source has dc content, and pre- vents unintentional power consumption when paus ing audio playback. the amplifier may be con- trolled using the eapd pi n (see eapd section.) using a vendor specific verb, the btl amplifier may be configured to support a mono speaker con- nected to the l +/- pins. in this mode, the left a nd right audio is mixed and sent to the left output only. the right channel is turned off to conserve power. maximum gain for the btl amplifier is programmab le. the following 4 gain se ttings relative to a nominal line output are desired: +6.5db, +9.5db, +14.5db, +16.5db. absolute gain may vary and the suggested accura cy is +/-1.5db. this gain is exposed in a vendor specific widge t and is intended to mimic the pin programmable gain implemented in discrete btl amplifiers commonly used in notebook computers. the btl amplifier includes thermal management circuitry. when the codec reaches a temperature of about 140 degrees, the output amplitude of the btl amp is gradually lowered until the tempera- ture falls below 140. all other functions will remain active if the btl amplifier is shut down due to die temperature. 2.18. btl amplifie r high-pass filter for mobile applications, speakers are often in capable of reproducing low frequency audio and unable to handle the maximum output power of th e btl amplifier. a high-pass filter is implemented www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 29 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec in the btl output path to reduce the amount of lo w frequency energy reaching speakers attached to the btl amplifier. this can prevent speaker failure. 2.18.1. filter description the high-pass filter is derived from the common biqu adratic filter and provides a 12db/octave roll-off. the filter may be programmed for a -3db response at: 100hz, 200hz, 300hz , 400hz, 500hz, 750hz, 1khz, or 2khz. the high pass filter is enabled by default with a cut-off frequen cy of 300hz. the filter may be bypassed using the associat ed verb (processi ng state verb). the analog pc_beep input is not affected by the digi tal high-pass filter. to ensure that the speakers attached to the btl amplifier are not harmed by low frequency audio entering the pc_beep input, an external filter must be implemented. fortunately, it is common practice to implement an attenuation circuit and dc blocking capacitor at the pc_beep input. this attenuator/filter is easily adjusted to restrict low frequency audio. the easiest approach is to reduce the value of the dc blocking capaci- tor but other approaches are equally effective. 2.19. eq there are 5 bands of parametric eq (bi-quad) per channel. due to th e flexibility of th e bi-quad imple- mentation, each filter band may be configured as a high-pass, low-pass, band-pass, high shelving, low shelving, or other function. each band has an independent set of coefficients. a bi-quad filter has 6 coefficients. one coefficient is normalized to 1 and 5 are programmed into the core. each band supports up to +15db boost or up to -36db cut. 2.20. combo jack detection 4 conductor (combo) jacks are becoming popular. in the most common implementation the 4 con- ductor plug has the same mechanical dimensions as a 3 conductor 3.5mm plug but the sleeve por- tion has been split into two segments:s1 and s2. wh en a 4-conductor plug (headset) is inserted into the jack t (tip) = left headphone audio, r (ring) = right headphone audio, s1 (first half of sleeve) = microphone input, and s2 (second half of sleeve) = return (gnd). when a 3-conductor plug (headphones) is inserted into the jack; t=left audio, r=right audio, s1 =gnd, s2=gnd. by moni- toring the s1 connection to see if it is shorted to ground, we can distinguish between headsets and headphones. please note that analog microphone plugs (3-conductor-lmic/rmic/gnd) and optical spdif plugs can not be support ed using this implementation. figure 10. combo jack g n d mi c www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 30 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec plug insertion is reported on the headphone po rt using the switch in tegrated into the jack. the internal circuit monitors the voltage at the jack to determine if a low impedance load is present. detection of a microphone is not reported unless plug insertion is also detected. 2.21. gpio 2.21.1. gpio pin mapping and shared functions 2.21.2. spdif/gpio selection 2 functions are available on the gpio3/spdifout (pin 40). to determine which function is enabled, the order of precedence is followed: 1. if the gpios are enabled, they override both spdif_out 2. if the gpios are not enabled through the afg, then at reset, the pin is pulled low by an internal pull-down resistor. 3. if the port is enable d as an output, the spd if output will be used. 2.21.3. digital microphone/gpio selection 2 functions are available on the dmic_clk/gpio1 (pin 2) and the dmic_0/gpio2 (pin 3) pins. to determine which function is enabled, the order of precedence is followed: 1. if gpios are not enabled through the afg, then at reset, pins 2,3 and 4 are pulled low by an internal pull-down resistor. 2. if the gpio 1 is enabled, the 2 dmic pins become mute (unless programmed for gpio or spdif use) and pin 3 becomes gpio with an internal pull-down. 3. if gpio2 is enabled through the afg, pin 4 becomes a gpio and is pulled low by an internal pull-down resistor. 4. if the port is en abled as an input, the di gital microphones will be used. 5. if the port is not enabled as an input or if the pin is configured as a gpio, the digital microphone path will be mute. 2.22. hd audio hda015-b support the codec provides complete su pport for the hda015-b specification (now dcn) building on the support already present in previous prod ucts. hda015-b features supported are: 1. persistence of many configuration options through bus and function group reset. 2. the ability to support port presen ce detect in d3 even when the hd audio bus is in a low power state (no clock.) 3. fast resume times from low power states: 1m s d1 to d0, 2ms d2 to d0, 10ms d3 to d0. gpio # pin supply spdif in spdif out gpi/o gpi gpo vrefout dmic vol pull up pull down 0 4 dvdd yes in 50k 1 2 dvdd yes clk 50k 2 3 dvdd yes in 50k 3 40 dvdd yes yes 50k www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 31 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 4. notification if persistent register settings have been unexpectedly reset. 5. spdif active in d3 (required) 2.23. digital core voltage regulator the digital core operates from a 1.8v (10%) supp ly voltage. many systems require that the codec use a single 3.3v digital supply, so an integrated regulator is included on die. the regulator uses pin 9, dvdd, as its voltage source. the output of the ldo is connected to pin 1 and the digital core. a 10uf capacitor must be placed on pin 1 for proper load regulation and regulator stability. the digital core voltage regulator is only dependent on dvdd. dvddio may be either 3.3 or 1.5v and may precede or follow dvdd in sequence. the codec digital logic and i/o (unless referenced to avdd) will operate in the absen ce of avdd. dvdd and avdd supp ly sequencing for the applica- tion of power and the removal of power is neither defined nor guaranteed. it is common for desktop systems to supply avdd from the system standb y supply and the codec will tolerate, indefinitely, the condition where avdd is active but dvdd and dvddio are inactive. 2.24. microphone mute input the 92HD95 supports a microphone mute input. an exte rnal switch or other circuit may directly mute the codec without rely ing on software control. this is a most helpful feature for allowing the end user to conveniently enforce priv acy since it bypasses the record gain/mute functions typically con- trolled by software. while reco rding is muted, any active st ream will receive digital silence. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 32 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 3. characteristics 3.1. electrical specifications 3.1.1. absolute maximum ratings stresses above the ratings lis ted below can cause permanent dam age to the 92HD95. these rat- ings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other condi tions above those indicated in the operational sec- tions of the specifications is not implied. expo sure to absolute maximu m rating conditions for extended periods can affect pro duct reliability. electrical parame ters are gua ranteed only over the recommended operating temperature range. 3.1.2. recommended operating conditions item pin maximum rating analog maximum supply voltage avdd 3.6 volts digital maximum supply voltage dvdd 3.6 volts btl maximum supply voltage pvdd 5.5 volts vrefout output current 5 ma voltage on any pin relative to ground vss - 0.3 v to vdd + 0.3 v operating temperature 0 o c to +70 o c storage temperature -55 o c to +125 o c soldering temperature soldering temperature information is available in the package section of this datasheet. table 16. electrical specification: maximum ratings parameter min. typ. max. units power supplies dvdd_core 1.62 1.8 1.98 v dvdd_io (3.3v signaling) 3.135 3.3 3.465 v dvdd_io (1.5v signaling) 1.418 1.5 1.583 v power supply voltage digital - 3.3 v 3.135 3.3 3.465 v analog - 3.3 v 3.135 3.3 3.465 v ambient operating temperature 0 +70 ? c case temperature t case (40-qfn) +90 ? c table 17. recommended operating conditions esd: the 92HD95 is an esd (electrostatic discharge) sens itive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 vo lts without detection. even though the 92HD95 implements internal esd protection circuitry, proper esd precautions sh ould be followed to avoid damaging the functionality or performance. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 33 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 3.2. 92HD95 analog perfor mance characteristics (preliminary) (t ambient = 25 oc, avdd = 3.3v +/-5%, dvdd = 3.3v 5% or 1.8v 10%, avss=dvss=0v; 20hz to 20khz swept sinu- soidal input; sample frequency = 48 khz; 0db fs = 1vrms for avdd = 4.75v and 0.71vrms for avdd = 3.3v, 10k ? //50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) parameter conditions min typ max unit digital to analog converters resolution 24 bits dynamic range 1 : pcm to all analog outputs -60db fs signal level, analog mixer disabled 93 db snr 2 - dac to all line-out ports analog mixer disabled, pcm data 95 db thd+n 3 - dac to all line-out ports analog mixer disabled,-3db fs signal, pcm data 82 dbr snr 2 - dac to all headphone ports analog mixer disabled, 10k ? load, pcm data 95 db thd+n 3 - dac to all headphone ports analog mixer disabled,-3db fs signal, 10k ? load, pcm data 65 dbr snr 2 - dac to all headphone ports analog mixer disabled, 32 ? load, pcm data 95 db thd+n 3 - dac to all headphone ports analog mixer disabled, -3db fs signal, 32 ? load, pcm data 68 dbr any analog input (adc) to dac crosstalk 10khz signal frequency. 0dbv signal applied to adc, dacs idle, ports enabled as output. -65 - - db any analog input (adc) to dac crosstalk 1khz signal frequency. see above -65 - - db dac l/r crosstalk dac to lo or hp 20-15khz into 10k ? load 70 73 db dac l/r crosstalk dac to hp 20-15khz into 32 ? load 65 68 db gain error analog mixer disabled 0.5 db interchannel gain mismatch analog mixer disabled 0.5 db d/a digital filter pass band 4 20 - 21,000 hz d/a digital filter pass band ripple 5 0.125 +/- db d/a digital filter transition band 21,000 - 31,000 hz d/a digital filter stop band 31,000 - - hz d/a digital filter stop band rejection 6 -100 - - db d/a out-of-band rejection 7 -55 - - db group delay (48khz sample rate) - - 1 ms attenuation, gain step size digital - 0.75 - db dac offset voltage - 10 20 mv deviation from linear phase - 1 10 deg. analog outputs full scale all outputs dac pcm data 1.00 - - vrms full scale all outputs dac pcm data 2.83 - - vp-p table 18. 92HD95 analog pe rformance characteristics www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 34 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec all headphone capable outputs 32 ?? load 40 60 - mw (peak) amplifier output impedance headphone outputs 150 0.1 ohms external load capacitance headphone outputs 220 pf analog inputs full scale input voltage 0db boost (input voltage required for 0db fs output) 1.05 - - vrms all analog inputs with boost 10db boost 0.320 - - vrms all analog inputs with boost 20db boost 0.105 - - vrms all analog inputs with boost 30db boost 0.032 - - vrms boost gain accuracy -2 2 db input impedance - 50 - k ? input capacitance - 15 - pf analog to digital converter resolution 24 bits full scale input voltage 0db boost (input voltage required to generate 0dbfs per aes 17) 1.05 dynamic range 1 , all analog inputs to a/d high pass filer enabled, -60db fs, no boost 86 db full scale input voltage 20db boost (input voltage required to generate 0dbfs per aes 17) 0.105 dynamic range 1 , all analog inputs to a/d 20db boost high pass filter enabled, -60db fs 80 db thd+n 3 all analog inputs to a/d high pass filter enabled, -1/-3db fs signal level 77 db thd+n 3 all analog inputs to a/d 20db boost, high pass filter enabled, -1/-3db fs signal level 72 db analog frequency response 8 10 - 30,000 hz a/d digital filter pass band 4 20 - 21,000 hz a/d digital filter pass band ripple 5 0.1 +/- db a/d digital filter transition band 21,000 - 31,000 hz a/d digital filter stop band 31,000 - - hz a/d digital filter stop band rejection 6 -100 - - db group delay 48 khz sample rate - - 1 ms any unselected analog input to adc crosstalk 10khz signal frequency -65 - - db any unselected analog input to adc crosstalk 1khz signal frequency -65 - - db adc l/r crosstalk any selected input to adc 20-15khz -65 db dac to adc crosstalk dac output 0dbfs. all outputs loaded. input to adc open. 20-15khz -65 db parameter conditions min typ max unit table 18. 92HD95 analog pe rformance characteristics www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 35 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec spurious tone rejection 9 - -100 - db attenuation, gain step size (analog) - 1.5 - db interchannel gain mismatch adc - - 0.5 db power supply power supply rejection ratio 10khz - tbd - db power supply rejection ratio 1khz - tbd - db d0 didd 10 3.3v, 1.8v tbd ma d0 aidd 10 3.3v tbd ma d2 didd 3.3v, 1.8v tbd ma d2 aidd 3.3v tbd ma d3cold didd 11 3.3v, 1.8v tbd ma d3cold aidd 11 3.3v tbd ma voltage reference outputs vrefout 12 - 0.5 x avdd - v vrefout drive 1.6 ma vrefilt (vag) 0.45 x avdd v phased locked loop pll lock time 96 200 usec pll (or hd audio bit clk) 24mhz clock jitter 150 500 psec esd / latchup iec1000-4-2 1 level jesd22-a114-b 2 class jesd22-c101 4 class 1.dynamic range is the ratio of the full scale signal to the noise output with a -60dbfs signal as defined in aes17 as snr in the presence of signal and outlined in aes6id, measured ?a weig hted? over 20 hz to 20 khz bandwidth 2.ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 3.thd+n ratio as defined in aes17 and outlined in aes6id ,non-weighted, over 20 hz to 20 khz bandwidth .results at the jack are dependent on external components and will likely be 1 - 2db worse. 4.peak-to-peak ripple over passband meets 0.125db limits, 48 khz or 44.1 khz sample frequency. 1db limit. 5. peak-to-peak ripple over passband m eets 0.125db limits, 48 khz or 44.1 khz sample frequency. 1db limit. 6.stop band rejection determines f ilter requirements. out-of-band re jection determines audible noise. 7.the integrated out-of-band nois e generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. 1db limits for line output & 0 db gain, at -20dbv 9.spurious tone rejection is test ed with adc dither enabled and compared to adc performance without dither. 10.one stereo dac and corresponding pin widgets enabled (playback mode) 11.idle measurement d3 set for minimum clicks/pops (biases and min. amps. on) 12.can be set to 0.5 or 0.8 avdd. parameter conditions min typ max unit table 18. 92HD95 analog pe rformance characteristics www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 36 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 3.3. class-d btl ampl ifier performance table 19. class-d btl amplifier performance parameter min typ max unit output power (btl 4 ohm, 5v, <1% thd+n) 2 w output power (btl 4 ohm, 5v, <10% thd+n) 3 w amplifier efficiency ?? (4 ? , 5v, 2w) 80 % thd+n (btl 4 ? , 5v, fs) 1% thd+n (btl 4 ? , 5v, -3dbfs) 0.3 % frequency response 20 - 20k hz pwm frequency 352.8 khz output voltage noise (4 ? , 5v) 90 uv idle current 15 ma shutdown current 0.1 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 37 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 3.4. capless headphone supply characteristics 3.5. ac timing specs 3.5.1. hd audio bus timing figure 11. hd audio bus timing parameter min typ max unit ldo idle current 1 2 ma capless headphone amp idle current 2 3 ma charge pump idle current 4 6 ma charge pump shutdown time 1 ms charge pump start-up time 10 ms frequency 384 khz c1/c2 cap value 2.2 uf table 20. capless headphone supply parameter definition symbol min typ max units bclk frequency average bclk frequency 23.9976 24.0 24.0024 mhz bclk period period of bclk including jitter tcyc 41.163 41.67 42.171 ns bclk high phase high phase of bclk t_high 17.5 24.16 ns bclk low phase low phase of bclk t_low 17.5 24.16 ns bclk jitter bclk jitter 150 500 ps sdi delay time after rising edge of bclk that sdi becomes valid t_tco 3 11 ns sdo setup setup for sdo at both rising and falling edges of bclk t_su 5 ns sdo hold hold for sdo at both rising and falling edges of bclk t_h 5 ns table 21. hd audio bus timing www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 38 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 3.5.2. spdif timing 3.5.3. digital microphone timing 3.5.4. gpio characteristics parameter definition symbol min typ max units spdif_out frequency highest rate of encoded signal 64 times the sample rate 2.8224 3.072 12.288 mhz spdif_out unit interval 1/(128 times the sample rate) ui 177.15 162.76 40.69 ns spdif_out jitter spdif_out jitter 4.43 ns spdif_out rise time t_rise 15 ns spdif_out fall time t_fall 15 ns table 22. spdif timing parameter definition symbol min typ max units dmic_clk frequency average dmic_c lk frequency 1.176 2.352 4.704 mhz dmic_clk period period of dmic_c lk tdmic_cyc 850.34 425.17 212.59 ns dmic_clk jitter dmic_clk jitter 5000 ps dmic data setup setup for the microphone data at both rising and falling edges of dmic_clk tdmic_su 5 ns dmic data hold hold for the microphone data at both rising and falling edges of dmic_clk tdmic_h 5 ns table 23. digital mic timing parameter definition symbol min typ max units input high voltage 1 1.high peak currents during dynamic switching of the class-d pwm outputs can result in gr ound rail bounce. the amount of ground bounce should be kept below 0.35 x vdd for all in puts, including internal logic which is tied to dvdd_core. input level at or above which a 1 is reliably recorded vih 0.6 x vdd v input low voltage 1 input level at or below which a 0 is reliably recorded. vdd may be dvdd or avdd vil 0.35 x vdd v output high voltage iout = 4ma vdd may be dvdd or avdd depending on pin voh 0.9 x vdd v output low voltage iout = -4ma vdd may be dvdd or avdd depending on pin vol 0.1 x vdd v input rise/fall time transition time between 10% and 90% of supply t_rise/t_fall 10 ns input/tristate high leakage current vin = vdd vdd may be dvdd or avdd depending on pin (does not include pull-up or pull-down resistor if present) 0.5 ua input/tristate low leakage current vin = 0 vdd may be dvdd or avdd depending on pin (does not include pull-up or pull-down resistor if present) -50 ua table 24. gpio characteristics www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 39 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 4. functional block diagram figure 12. functional block diagram stream & channel select dac 0 stream & channel select stream & channel select hd audio link logic pcm to spdif out spdif out0 vol dac 1 digital mute digital mute vendor specific mux adc0 pin 40 pin 3 dmic_0 dmic_0 mux adc1 mux stream & channel select digital microphone volume and mute is done after the adc but shown here and in widget list as same as analog path. dac0 dac1 boost +0/+10/+20/+30 db dmic adc0 stream & channel select vol gain mute -16 to +30 db in 1 db steps adc1 vol gain mute -16 to +30 db in 1 db steps vol pin complex pins 13/14 port c mic bias pin complex pins 32/33/35/36 port d boost +0/+10/+20/+30 db port c btl class-d pin complex pins 16/17 port b boost +0/+10/+20/+30 db port b pin complex pins 22/23 port a hp cap-less ? analog beep mic bias mux digital pc beep dac1 dac0 digital pwm controller ? analog beep_dig dac1_dig dac0_dig highpass filter 5-band eq clocking mux digital pc beep vol mute analog pc_beep 0,-6,-12,-18db vol mute 0,-6,-12,-18db detect/convert analog beep analog beep_dig beep_active mux port mux dmic0 port mux dac0 dac1 dmic1 mux dmic0 port mux dac0 dac1 dmic1 mux pin 38 dmic_1 dmic_0 boost +0/+10/+20/+30 db dmic www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 40 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 5. widget diagram figure 13. widget diagram hda link adc0 mux adc1 mux dac0 adc0 nid = 12h dmic0 nid = 0eh port b port a nid = 0ah analog* dac0 nid = 10h volume mute hp nid = 14h adc0 mux volume mute dmic0 dac1 nid = 15h vol adc1 nid = 13h dac1 nid = 0bh port c bias nid = 0ch port d nid = 0dh dac1 nid = 11h volume mute 10/20/30 -16 to 30db 1db step -95.25 to 0db 0.75db step -95.25 to 0db 0.75db step pc_beep nid = 19h digital btl pc_beep (pin 12) mute volume dac0 dac1 in vol 10/20/30 port mux adc1 mux volume mute -16 to 30db 1db step port c 0,-6,-12,-18db vsv dac0 dac1 dmic0 d ? nodes are digital capable dmic0 port mux port b to all ports enabled as an output to all ports enabled as an output bias in vol 10/20/30 spdif out0 nid = 17h nid = 18h dig0pin adc1 mux digital adc0 mux vendor specific test d d dac0 dac1 dac0 nid = 16h port mux port c port b port mux dmic1 nid = 0fh analog* vol 10/20/30 dmic1 dmic1 dmic1 nid = 1ah vsw www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 41 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 6. port and pin configurations 6.1. port configurations figure 14. port configurations b mic,hp hp a front desktop 2 b hp rear c mic hp a front desktop chassis speaker d a mic / li /hp hp / lo b side internal mic c mobile a m p chassis speaker d a m p internal speakers d a m p spdif_out or dmic spdif_out spdif_out www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 42 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 6.2. pin configuration defa ult register settings the following table shows the pin widget configuration defa ult settings. desktop implementation with 2 jacks in front and 1 jack in rear. the internal speaker is redirected from the front (green) headphone jack. an internal microphone is present. pin name port location device connection color misc assoc. seq portapin connect to jack 00b mainboard right 4h hp out 2h 1/8 inch jack 1h green 4h jack detect override=0 1h 0h portbpin connect to jack 00b mainboard right 4h mic in ah 1/8 inch jack 1h pink 9h jack detect override=0 2h 0h portcpin no connect 01b na rear 0h other fh unknown 0h unknown 0h jack detect override=0 fh 0h portdpin internal 10b na 010000b speaker 1h other analog 7h unknown 0h jack detect override=1 3h 0h digoutpin0 no connect 01b na 0h other fh unknown 0h unknown 0h jack detect override=0 fh 0h digmic0pin internal 10b internal 010000b mic in ah atapi 3h unknown 0h jack detect override=1 4h 0h digmic1pin no connect 01b na 0h other fh unknown 0h unknown 0h jack detect override=0 fh 0h table 25. pin configuration default settings www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 43 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7. widget information there are two types of responses: solicited and un solicited. solicited responses are provided as a direct response to an issued command and will be provided in the frame immediately following the command. unsolicited responses are provided by the codec independent of any command. unso- licited responses are the result of codec events su ch as a jack insertion detection. the formats for solicited responses and un solicited responses are shown in the tables below. the ?tag? field in bits [31:28] of the unsolicited response identify the event. bits [39:32] bits [31:28] bits [27:20] bits[19:16] bits [15:0] reserved codec address nid verb id (4-bit) payload data (16-bit) table 26. command format for verb with 4-bit identifier bits [39:32] bits [31:28] bits [27:20] bits[19:8] bits [7:0] reserved codec address nid verb id (12-bit) payload data (8-bit) table 27. command format for verb with 12-bit identifier bit [35] bit [34] bits [33:32] bits[31:0] valid (valid = 1) unsol = 0 reserved response table 28. solicited response format bit [35] bit [34] bits [33:32] bits[31:28] bits [27:0] valid (valid = 1) unsol = 1 reserved tag response table 29. unsolicited response format www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 44 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.1. widget list table 30. widget list id widget name description 00h root root node 01h afg audio function group 0ah port a port a pin widget (cap-less headphone, line out) 0bh port b port b pin widget (line in, mic+ vrefout) 0ch port c port c pin widget (line in, mic+ vrefout) 0dh port d port d pin widget (class-d btl output) 0eh digmic0 digital microphone 0 pin widget 0fh digmic1 digital microphone 1 pin widget 10h dac0 stereo output converter to dac 11h dac1 stereo output converter to dac 12h adc0 stereo input converter to adc 13h adc1 stereo input converter to adc 14h adc0mux adc0 mux with volume and mute 15h adc1mux adc1 mux with volume and mute 16h port mux port b/c selector 17h spdifout0 stereo output for spdif_out 18h dig0pin digital output pin (pin40) 19h pcbeep digital pc beep 1ah vsw btl register access www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 45 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.2. reset key abbreviation description por power on reset. safg single afg reset - one single write to the reset verb in the afg node. dafg double afg reset - two consecutive single afg resets with only idle frames (if any) and no link resets between. s&dafg single and double afg reset - either one will cause reset. lr link reset - level sensitive reset anytime the hda reset is set low. elr exiting link reset - edge sensitive reset any time the hda reset transitions from low to high. ulr unexpected link reset - level sensitive reset anytime the hda reset is set low when the clkstopok indicator is currently set to 0. ps power state change - reset anytime the actual power state changes for the widget in question. 7.3. root (nid = 00h): vendorid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0000h field name bits r/w default reset vendor 31:16 r 111dh n/a vendor id. devicefix 15:8 r see below n/a device id. deviceprog 7:0 r see below n/a device id. device 92HD95 device id 7695h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 46 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.3.1. root (nid = 00h): vendorid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0000h field name bits r/w default reset vendor 31:16 r 111dh n/a (hard-coded) vendor id. devicefix 15:8 r 76h n/a (hard-coded) fixed portion of device id. deviceprog 7:0 r 95h n/a (hard-coded) programmable portion of device id (top 4 bits in metal, bottom 4 bits by bond option. 7.3.2. root (nid = 00h): revid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0002h field name bits r/w default reset rsvd 31:24 r 00h n/a (hard-coded) reserved. major 23:20 r 1h n/a (hard-coded) major rev number of compliant hd audio spec. minor 19:16 r 0h n/a (hard-coded) minor rev number of compliant hd audio spec. revisionfix 15:12 r xh n/a (hard-coded) vendor's rev number for this device. revisionprog 11:8 r xh n/a (hard-coded) vendor's rev number for this device. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 47 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec steppingfix 7:4 r xh n/a (hard-coded) vendor stepping number within the vendor revid. steppingprog 3:0 r xh n/a (hard-coded) vendor stepping number within the vendor revid. 7.3.3. root (nid = 00h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. startnid 23:16 r 01h n/a (hard-coded) starting node number (nid) of first function group rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 01h n/a (hard-coded) total number of nodes 7.4. afg (nid = 01h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 48 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec startnid 23:16 r 0ah n/a (hard-coded) starting node number for function group subordinate nodes. rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 11h n/a (hard-coded) total number of nodes. 7.4.1. afg (nid = 01h): fgtype reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0005h field name bits r/w default reset rsvd 31:9 r 000000h n/a (hard-coded) reserved. unsol 8 r 1h n/a (hard-coded) unsolicited response supported: 1 = yes, 0 = no. nodetype 7:0 r 1h n/a (hard-coded) function group type: 00h = reserved 01h = audio function group 02h = vendor defined modem function group 03h-7fh = reserved 80h-ffh = vendor defined function group 7.4.2. afg (nid = 01h): afgcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0008h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 49 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd3 31:17 r 00h n/a (hard-coded) reserved. beepgen 16 r 1h n/a (hard-coded) beep generator present: 1 = yes, 0 = no. rsvd2 15:12 r 0h n/a (hard-coded) reserved. inputdelay 11:8 r dh n/a (hard-coded) typical latency in frames. number of samples between when the sample is re- ceived as an analog signal at the pin and when the digital representation is transmitted on the hd audio link. rsvd1 7:4 r 0h n/a (hard-coded) reserved. outputdelay 3:0 r dh n/a (hard-coded) typical latency in frames. number of samples between when the signal is re- ceived from the hd audio link and when it appears as an analog signal at the pin. 7.4.3. afg (nid = 01h): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 50 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 51 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 7.4.4. afg (nid = 01h): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 0h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 7.4.5. afg (nid = 01h): inampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000dh field name bits r/w default reset mute 31 r 0h n/a (hard-coded) mute support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 52 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 27h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 7.4.6. afg (nid = 01h): pwrstatecap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000fh field name bits r/w default reset epss 31 r 1h n/a (hard-coded) extended power states support: 1 = yes, 0 = no. clkstop 30 r 1h n/a (hard-coded) d3 clock stop support: 1 = yes, 0 = no. s3d3coldsup 29 r 1h n/a (hard-coded) codec state intended during system s3 state: 1 = d3hot, 0 = d3cold. rsvd 28:5 r 000000h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 53 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec d3coldsup 4 r 1h n/a (hard-coded) d3cold power state support: 1 = yes, 0 = no. d3sup 3 r 1h n/a (hard-coded) d3 power state support: 1 = yes, 0 = no. d2sup 2 r 1h n/a (hard-coded) d2 power state support: 1 = yes, 0 = no. d1sup 1 r 1h n/a (hard-coded) d1 power state support: 1 = yes, 0 = no. d0sup 0 r 1h n/a (hard-coded) d0 power state support: 1 = yes, 0 = no. 7.4.7. afg (nid = 01h): gpiocnt reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0011h field name bits r/w default reset gpiwake 31 r 1h n/a (hard-coded) wake capability. assuming the wake enable mask controls are enabled, gpio's configured as inputs can cause a wake (generate a status change event on the link) when there is a change in level on the pin. gpiunsol 30 r 1h n/a (hard-coded) gpio unsolicited response support: 1 = yes, 0 = no. rsvd 29:24 r 00h n/a (hard-coded) reserved. numgpis 23:16 r 00h n/a (hard-coded) number of gpi pins supported by function group. numgpos 15:8 r 00h n/a (hard-coded) number of gpo pins supported by function group. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 54 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec numgpios 7:0 r 04h n/a (hard-coded) number of gpio pins supported by function group. 7.4.8. afg (nid = 01h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 02h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 7fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 7fh n/a (hard-coded) indicates which step is 0db 7.4.9. afg (nid = 01h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 55 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd3 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this function group have been reset. cleared by pwrstate 'get' to this widget. clkstopok 9 r 1h por - dafg - ulr bit clock can currently be removed: 1 = yes, 0 = no. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7 r 0h n/a (hard-coded) reserved. act 6:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3 r 0h n/a (hard-coded) reserved. set 2:0 rw 3h por - dafg - lr current power state setting for this widget. 7.4.10. afg (nid = 01h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable: 1 = enabled, 0 = disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 56 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.4.11. afg (nid = 01h): gpio reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 715h get f1500h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. data3 3 rw 0h por - dafg - ulr data for gpio3. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data2 2 rw 0h por - dafg - ulr data for gpio2. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data1 1 rw 0h por - dafg - ulr data for gpio1. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data0 0 rw 0h por - dafg - ulr data for gpio0. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 57 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.4.12. afg (nid = 01h): gpioen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 716h get f1600h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. mask3 3 rw 0h por - dafg - ulr enable for gpio3: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask2 2 rw 0h por - dafg - ulr enable for gpio2: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask1 1 rw 0h por - dafg - ulr enable for gpio1: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask0 0 rw 0h por - dafg - ulr enable for gpio0: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control 7.4.13. afg (nid = 01h): gpiodir reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 717h get f1700h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 58 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec control3 3 rw 0h por - dafg - ulr direction control for gpio3: 0 = gpio is configured as input; 1 = gpio is con- figured as output control2 2 rw 0h por - dafg - ulr direction control for gpio2: 0 = gpio is configured as input; 1 = gpio is con- figured as output control1 1 rw 0h por - dafg - ulr direction control for gpio1: 0 = gpio is configured as input; 1 = gpio is con- figured as output control0 0 rw 0h por - dafg - ulr direction control for gpio0: 0 = gpio is configured as input; 1 = gpio is con- figured as output 7.4.14. afg (nid = 01h): gpiowakeen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 718h get f1800h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. w3 3 rw 0h por - dafg - ulr wake enable for gpio3: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w2 2 rw 0h por - dafg - ulr wake enable for gpio2: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w1 1 rw 0h por - dafg - ulr wake enable for gpio1: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 59 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec w0 0 rw 0h por - dafg - ulr wake enable for gpio0: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. 7.4.15. afg (nid = 01h): gpiounsol reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 719h get f1900h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. enmask3 3 rw 0h por - dafg - ulr unsolicited enable mask for gpio3. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask2 2 rw 0h por - dafg - ulr unsolicited enable mask for gpio2. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask1 1 rw 0h por - dafg - ulr unsolicited enable mask for gpio1. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio1 is configured as input and changes state. enmask0 0 rw 0h por - dafg - ulr unsolicited enable mask for gpio0. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio0 is configured as input and changes state. 7.4.16. afg (nid = 01h): gpiosticky reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71ah field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 60 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec get f1a00h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. mask3 3 rw 0h por - dafg - ulr gpio3 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask2 2 rw 0h por - dafg - ulr gpio2 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask1 1 rw 0h por - dafg - ulr gpio1 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask0 0 rw 0h por - dafg - ulr gpio0 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). 7.4.17. afg (nid = 01h): subid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 723h 722h 721h 720h get f2300h / f2200h / f2100h / f2000h field name bits r/w default reset subsys3 31:24 rw 00h por subsystem id (byte 3) subsys2 23:16 rw 00h por subsystem id (byte 2) subsys1 15:8 rw 01h por subsystem id (byte 1) 7.4.16. afg (nid = 01h): gpiosticky reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 61 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec assembly 7:0 rw 00h por assembly id (not applicable to codec vendors). 7.4.18. afg (nid = 01h): gpioplrty reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 770h get f7000h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. gp3 3 rw 1h por gpio3 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp2 2 rw 1h por gpio2 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp1 1 rw 1h por gpio1 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 62 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec gp0 0 rw 1h por gpio0 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected 7.4.19. afg (nid = 01h): gpiodrive reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 771h get f7100h field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. od3 3 rw 0h por gpio3 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od2 2 rw 0h por gpio2 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od1 1 rw 0h por gpio1 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od0 0 rw 0h por gpio0 drive mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float for 1). 7.4.20. afg (nid = 01h): dmic reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 778h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 63 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec get f7800h field name bits r/w default reset rsvd 31:6 r 0000000h n/a (hard-coded) reserved. mono1 5 rw 0h por dmic1 mono select: 0 = stereo operati on, 1 = mono operation (left channel du- plicated to the right channel). mono0 4 rw 0h por dmic0 mono select: 0 = stereo operati on, 1 = mono operation (left channel du- plicated to the right channel). phadj 3:2 rw 0h por selects what phase of the dmic clock the data should be latched: 0h = left data rising edge/right data falling edge 1h = left data center of high/right data center of low 2h = left data falling edge/right data rising edge 3h = left data center of low/right data center of high rate 1:0 rw 2h por selects the dmic clock rate: 0h = 4.704mhz 1h = 3.528mhz 2h = 2.352mhz 3h = 1.176mhz. 7.4.21. afg (nid = 01h): dacmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 781h 780h get f8100h / f8000h field name bits r/w default reset rsvd 31:9 r 000000h n/a (hard-coded) reserved. 7.4.20. afg (nid = 01h): dmic reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 64 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec swapen 8 rw 0h por internal dac left channel and right channel swap. 0h = not swap, 1h = swap. sdmsettledisable 7 rw 0h por sdm wait-to-settle disable: 1 = at mute, the sdm switches to the mute pattern immediately 0 = at mute, the sdm switches to the mute pattern after settling (can take up to ~45ms) sdmcoeffsel 6 rw 0h por dac sdm coefficient select (stages 1, 2, 3): 1 = 1/16, 1/2, 1/4 0 = 1/16, 1/4, 1/2 sdmlfhalf 5 rw 0h por dac sdm local feedback coefficient select: 1 = 1/4096, 0 = 1/2048. sdmlfdisable 4 rw 0h por dac sdm local feedback disable: 1 = local feedback disabled, 0 = local feed- back enabled. invertvalid 3 rw 0h por dac valid invert: 1 = 7.056mhz valid strobe is inverted, 0 = 7.056mhz valid strobe is not inverted. invertdata 2 rw 0h por dac data invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert- ed. atten6dbdisable 1 rw 1h por disable built-in -6db digital attenuation: 1 = -6db disabled, 0 = -6db enabled. fade 0 rw 1h por dac gain fade enable: 1 = gain will be slowly faded from old value to new value (~10ms) 0 = gain will jump immediately to new value. 7.4.22. afg (nid = 01h): adcmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 784h get f8400h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 65 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:5 r 0000000h n/a (hard-coded) reserved. adcgainsel 4 rw 0h por adc boost gain selection: 1 = 1db, 0 = 3db. invertvalid 3 rw 0h por adc valid invert: 1 = 14.112mhz valid strobe is inverted, 0 = 14.112mhz valid strobe is not inverted. invertdata 2 rw 0h por adc data invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted. adcclkdelay 1 rw 0h por delay adc clock. dacclkdelay 0 rw 0h por delay dac clock. 7.4.23. afg (nid = 01h): eapd reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 78ah 789h 788h get f8a00h / f8900h / f8800h field name bits r/w default reset rsvd3 31:11 r 000000h n/a (hard-coded) reserved. hpasdinv 10 rw 0h por port a hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpasdmode 9 rw 1h por port a hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 66 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec hpasd 8 rw 0h por port a hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd2 7 r 0h n/a (hard-coded) reserved. btlsdinv 6 rw 0h por btl amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high btlsdmode 5 rw 1h por btl amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled btlsd 4 rw 0h por btl amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd1 3:2 r 0h n/a (hard-coded) reserved. pinmode 1:0 rw 0h por eapd pin mode: 00b = open drain i/o (value at pin is wi red-and of eapd bit & external signal) 01b = cmos output (value of eapd bit is forced at pin) 1xb = cmos input (external signal cont rols internal amps, eapd bit ignored) 7.4.24. afg (nid = 01h): portuse reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c0h get fc000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 67 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:4 r 0000000h n/a (hard-coded) reserved. portd 3 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable. portc 2 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable portb 1 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable porta 0 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable. 7.4.25. afg (nid = 01h): comjack reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c7h 7c6h get fc700h/fc600h field name bits r/w default reset rsvd3 31:11 r 00000000h n/a (hard-coded) reserved. rbcon 10:8 rw 4h por combo jack detection reference voltage 000 = 0.18*avdd 001 = 0.16*avdd 010 = 0.14*avdd 011 = 0.12*avdd 100 = 0.10*avdd 101 = 0.08*avdd 110 = 0.06*avdd 111 = 0.04*avdd www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 68 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec masterport 7:5 rw 0h por port tied to the jack presence detection switch 000 = port a 001 = port b 010 = port c 011 = port d 100 = port e 101 = port f rsvd1 4 r 0h n/a (hard-coded) reserved. slaveport 3:1 rw 0h por port used as microphone input when combo jack detection is enabled, port presence detection as shown in the pin complex is not sensed directly by the sense input but is inferred by the load placed on the vref_output associated with the port 000 = port a 001 = port b 010 = port c 011 = port d;100 = port e 101 = port f det-en 0 r 0h por 0h = disable combo jact detection 1h = enable combo jact detection 7.4.26. afg (nid = 01h): combojacktime reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7cah 7c9h get fca00h/fc900h field name bits r/w default reset rsvd3 31:16 r 0000h n/a (hard-coded) reserved. bouncertimer_bypass 15 rw 0h por 0 = all the combjack debounce time in normal; 1= all the comjack debounce time in simulation mode(debounce time is short). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 69 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec t_delay_slave_port_usr 14:12 rw 3h por 000 = 2frame 001 =4frame 010 =8frame 011 =16frame 100 = 32frame 101 =64frame 110 = 128frame 111 = 256frame t_stable 11:8 rw 6h por 0000 = 0.1ms 0001 =0.5ms 0010 =1ms 0011 =2ms 0100 = 4ms 0101 =8ms 0110 = 16ms 0111 = 32ms 1000 = 64ms 1001 =128ms;1010 =256ms;1011 =512ms 1100 = 1024ms 1101 =1024ms 1110 = 1024ms 1111 = 1024ms rsvd2 7 r 0h n/a (hard-coded) reserved t_long_realtime_detect 6:4 rw 5h por 000 = 2s 001 =4s 010 =8s 011 =16s 100 = 32s 101 =64s 110 = 128s 111 = infinite rsvd1 3 r 0h n/a (hard-coded) reserved field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 70 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec t_delay_verfout 2:0 rw 3h por 000 = 0.1ms 001 =50ms 010 = 125ms 011 =250ms 100 = 500ms 101 = 1s 110 = 2s 111 = 4s 7.4.27. afg (nid = 01h): vspwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7d8h get fd800h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. d5 1 rw 0h por - elr vendor specific d5 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if set, this bit over- rides the d4 bit (bit 0). includes the power savings of d4, but additionally pow- ers down gpio pins, the vag amp, and the hp amps. exits this power state via por or rising edge of link reset. d4 0 rw 0h por - elr vendor specific d4 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if the d5 bit (bit 1) is set, this bit is overridden. includes the power savings of d3cold, but addi- tionally powers down the hda interface (no responses). exit this power state via por or rising edge of link reset. 7.4.28. afg (nid = 01h): anaport reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7ech get fec00h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 71 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:4 r 0000000h n/a (hard-coded) reserved. dpwd 3 rw 0h por power down port d. cpwd 2 rw 0h por power down port c. bpwd 1 rw 0h por power down port b. apwd 0 rw 0h por power down port a. 7.4.29. afg (nid = 01h): anabeep reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7efh 7eeh get fee00h / fee00h field name bits r/w default reset rsvd2 31:14 r 00000h n/a (hard-coded) reserved. detect 13 r 0h por - dafg - ulr 0: no beep present; 1: beep present. gainadj 12:10 rw 3h por analog pc beep gain in digital side 7h = -6db, 6h = -12db, 5h = -18db, 4h = -24db, 3h = -30db, 2h = -36db, 1h = -42db, 0h = -48db. converten 9 rw 1h por analog pc beep quantization enable (enabled only when both ""d2a_ana_pc_beep_det_en"" and ""d2a_ana_pc_beep_convert_en"" are 1). detecten 8 rw 1h por analog pc beep detection enable 0h = disable 1h = enable. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 72 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd1 7:6 r 0h n/a (hard-coded) gain 5:4 rw 3h por analog pc beep gain: 0h = -24db, 1h = -18db, 2h = -12db, 3h = -6db. cntsel 3:2 rw 0h por select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms. mode 1:0 rw 2h por analog pc beep mode: 00b = always disabled 01b = always enabled 1xb = enabled during hda link reset only 7.4.30. afg (nid = 01h): anabtl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7f6h 7f5h 7f4h get ff600h / ff500h / ff400h field name bits r/w default reset rsvd6 31:22 r 000h n/a (hard-coded) reserved. scstabletimesel 21:20 rw 0h por the programmed time window for short circuit detect. tsoverridehiz 19 rw 0h por override hiz for the btl amplifier power stage circuit: set to 1 to hiz, set back to 0 to normal mode tstestmode 18 rw 0h por temp sense test mode select, 0=normal operation, 1=sensor will trip at ambi- ent temperature. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 73 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec tsforcepwd 17 rw 1h por temp sense force powerdown select 0=btl will not be muted and powered down even if it is still overheating when the volume is 0h 1=btl will be muted and powered down even if it is still overheating when the volume is 0h tsinstantcutmode 16 rw 0h por temp sense instant cut mode 0=two trip points used to smoothly adjust the volume 1=one single trip point used to set volume to wither 0 or max value (ti mode) tswait 15:12 rw 3h por temperature sensing wait time between volume increments 0h = 2ms (polling at 2ms) 1h = 4ms (polling at 4ms) 2h = 8ms (polling at 8ms) 3h = 16ms (polling at 16ms) 4h = 32ms (polling at 16ms) 5h = 64ms (polling at 16ms) 6h = 128ms (polling at 16ms) 7h = 256ms (polling at 16ms) 8h = 512ms (polling at 16ms) 9h = 1.024s (polling at 16ms) ah = 2.048s (polling at 16ms) bh = 4.096s (polling at 16ms) ch = 8.192s (polling at 16ms) dh = 16.384s (polling at 16ms) eh = 32.768s (polling at 16ms) fh = 65.536s (polling at 16ms). tstriphish 11:9 rw 3h por temp sense high trip point setting: 0h = 125 degrees c 1h =140 degrees c 2h = 155 degrees c 3h = 170 degrees c 4h = 185 c 5h = 200 c 6h = 215 c 7h = reserved tsoverriderest 8 rw 0h por override reset for the btl amplifier temp se nse circuit: set to 1 to recalculate, set back to 0 to latch the value field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 74 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec tstriplow 7:5 rw 2h por temp sense low trip point setting: 0h = 110 degrees c 1h = 125 degrees c 2h = 140 degrees c 3h = 155 degrees c 4h = 170 c 5h = 185 c 6h = 200 c 7h = 215 c classdmono 4 rw 0h por config btl to mono mode. 0:stereo 1:mono monospkvolselen 3 rw 0h por btl right channel spkvol selection enable under mono mode. 0:keep right channel spkvol; 1:select le ft channel spkvol. dcbypass 2 rw 0h por 1 = bypass btl dc filter rsvd1 1:0 r 0h na reserved 7.4.31. afg (nid = 01h): anabtlstatus reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get ff700h field name bits r/w default reset rsvd1 31:20 r 000h n/a (hard-coded) reserved. tstriphigh 19 r 0h por temp sense high trip point status tstriplow 18 r 0h por temp sense low trip point status field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 75 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec tsmute 17 r 0h por temp sense forced mute status for btl amplifier tspwd 16 r 0h por temp sense forced powerdown status for btl amplifier tsleftvol 15:8 r ffh por temp sense volume status for the btl amplifier: 00000000b..11111111b = range specified for spkvol field. tsrightvol 7:0 r ffh por temp sense volume status for the btl amplifier: 00000000b..11111111b = range specified for spkvol field. 7.4.32. afg (nid = 01h): anacapless reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7fbh 7fah 7f9h 7f8h get ffb00h / ffa00h / ff900h / ff800h field name bits r/w default reset rsvd4 31 r 0h n/a (hard-coded) reserved. pwdanamd 30 rw 1h por power down analog select block. anaselen 29 rw 0h por 1=enable analog select mode, 0=enable digital select mode. mdlevsel 28 rw 0h por 1=selct high threshold level of analog mode, 0=select low threshold level of analog mode clasgbypass 27 rw 0h por 0=clasg enable, 1=bypass clasg, only class ab work field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 76 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 26 r 0h n/a (hard-coded) reserved. vregscdet 25 r 0h por capless regulator short circuit detect indicator. chargepumpscdet 24 r 0h por capless charge pump short circuit detect indicator. vregsel 23:20 rw 5h por capless regulator output voltage multiply ratio bits [3..2] reserved bits [1..0]: 00b = 2*vbg 01b = 2.1*vbg 10b = 2.2*vbg 11b = 2.3*vbg vregscrstb 19 rw 0h por capless regulator short circuit detect rese t: 0 = short circuit detect disabled, 1 = short circuit detect enabled. vreggndshort 18 rw 0h por ground the capless regulator output. vregpwd 17 rw 0h por capless regulator powerdown. chargepumpscrstb 16 rw 0h por capless charge pump short circuit detect reset: 0 = short circuit detect dis- abled, 1 = short circuit detect enabled. chargepumphiz 15 rw 0h por hi-z the capless charge pump outputs. chargepumppwd 14 rw 0h por capless charge pump powerdown. chargepumpsplydetover- ride 13 rw 0h por capless charge pump supply detect override. rsvd2 12 r 0h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 77 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec chargepumpclkrate 11:8 rw 8h por capless charge pump clock rate: 0000b = 800.0khz (24mhz/30) 0001b = 750.0khz (24mhz/32) 0010b = 706.9khz (24mhz/34) 0011b = 666.7khz (24mhz/36) 0100b = 631.6khz (24mhz/38) 0101b = 600.0khz (24mhz/40) 0110b = 571.4khz (24mhz/42) 0111b = 545.5khz (24mhz/44) 1000b = 800.0khz (24mhz/30) 1001b = 857.1khz (24mhz/28) 1010b = 923.1khz (24mhz/26) 1011b = 1.000mhz (24mhz/24) 1100b = 1.091mhz (24mhz/22) 1101b = 1.200mhz (24mhz/20) 1110b = 1.333mhz (24mhz/18) 1111b = 1.500mhz (24mhz/16) chargepumpclkdiv 7:5 rw 4h por capless charge pump analog clock divider: 001b = no divide 010b = divide by 2, 50% duty cycle 100b = divide by 4, 50% duty cycle 110b = divide by 2, 75% duty cycle 011b = divide by 4, 75% duty cycle 111b = divide by 4, 87.5% duty cycle other values undefined chargepumpclksel 4 rw 0h por capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock defined by afgcaplesschargepumpclkrate[3:0] field below. padgnd 3 rw 0h por ground the output pad of the capless amplifiers. inputgnd 2 rw 0h por ground the input to the capless output amplifiers. rsvd1 1 r 0h na reserved antipopbypass 0 rw 0h por 0 = enable anti-pop on the capless headphone; 1 = bypass anti-pop on the ca- pless headphone. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 78 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.4.33. afg (nid = 01h): reset reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7ffh get fff00h field name bits r/w default reset rsvd1 31:8 r 000000h n/a (hard-coded) reserved. execute 7:0 w 00h n/a (hard-coded) function reset. function group reset is executed when the set verb 7ff is written with 8-bit payload of 00h. the codec should issue a response to ac- knowledge receipt of the verb, and then reset the affected function group and all associated widgets to their power-on reset values. some controls such as configuration default controls should not be reset. overlaps response. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 79 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.5. porta (nid = 0ah): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 80 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.5.1. porta (nid = 0ah): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 81 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.5.2. porta (nid = 0ah): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 82 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 02h n/a (hard-coded) number of nid entries in connection list. 7.5.3. porta (nid = 0ah): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) reserved. conl2 23:16 r 00h n/a (hard-coded) reserved. conl1 15:8 r 11h n/a (hard-coded) dac1 converter widget (0x11) conl0 7:0 r 10h n/a (hard-coded) dac0 converter widget (0x10) 7.5.4. porta (nid = 0ah): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 83 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:1 r 00000000h n/a (hard-coded) reserved. index 0 rw 0h por - dafg - ulr connection select control index. 7.5.5. porta (nid = 0ah): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 84 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.5.6. porta (nid = 0ah): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 r 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 r 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 7.5.7. porta (nid = 0ah): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 85 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.5.8. porta (nid = 0ah): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.5.9. porta (nid = 0ah): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 86 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.5.10. porta (nid = 0ah): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 87 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec location 29:24 rw 04h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw 2h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 88 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 4h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 1h por default association. sequence 3:0 rw 0h por sequence. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 89 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.6. portb (nid = 0bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 90 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.6.1. portb (nid = 0bh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 91 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefcntrl 15:8 r 17h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.6.2. portb (nid = 0bh): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 92 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.6.3. portb (nid = 0bh): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.6.4. portb (nid = 0bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 93 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.6.5. portb (nid = 0bh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 5:0 rw 00h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 94 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 7.6.6. portb (nid = 0bh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.6.7. portb (nid = 0bh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 95 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.6.8. portb (nid = 0bh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.6.9. portb (nid = 0bh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 96 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 04h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 97 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 9h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 2h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 98 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.7. portc (nid = 0ch): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 99 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.7.1. portc (nid = 0ch): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 100 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefcntrl 15:8 r 17h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.7.2. portc (nid = 0ch): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 101 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.7.3. portc (nid = 0ch): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.7.4. portc (nid = 0ch): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 102 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.7.5. portc (nid = 0ch): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. outen 6 r 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 103 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 7.7.6. portc (nid = 0ch): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.7.7. portc (nid = 0ch): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 104 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.7.8. portc (nid = 0ch): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.7.9. portc (nid = 0ch): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 105 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset portconnectivity 31:30 rw 1h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 00h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw fh por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 106 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connectiontype 19:16 rw 0h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw fh por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 107 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.8. portd (nid = 0dh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 108 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.8.1. portd (nid = 0dh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 109 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 1h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.8.2. portd (nid = 0dh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 110 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 02h n/a (hard-coded) number of nid entries in connection list. 7.8.3. portd (nid = 0dh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) reserved conl2 23:16 r 00h n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 11h n/a (hard-coded) dac1 converter widget (0x11) conl0 7:0 r 10h n/a (hard-coded) dac0 converter widget (0x10) 7.8.4. portd (nid = 0dh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 111 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 0 rw 0h por - dafg - ulr connection select control index. 7.8.5. portd (nid = 0dh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 112 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.8.6. portd (nid = 0dh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. hphnen 7 r 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 r 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 0h n/a (hard-coded) reserved. 7.8.7. portd (nid = 0dh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 113 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.8.8. portd (nid = 0dh): esdrest reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 780h get f8000h field name bits r/w default reset rsvd1 31:1 r 00000000h n/a (hard-coded) reserved. execute 0 w 0h n/a (hard-coded) reset_b the esd trigger block. low active. 7.8.9. portd (nid = 0dh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 114 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw 1h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 115 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connectiontype 19:16 rw 7h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 3h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 116 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.9. dmic0 (nid = 0eh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 117 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.9.1. dmic0 (nid = 0eh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 118 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hphndrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.9.2. dmic0 (nid = 0eh): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 119 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.9.3. dmic0 (nid = 0eh): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.9.4. dmic0 (nid = 0eh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 120 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.9.5. dmic0 (nid = 0eh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:6 r 0000000h n/a (hard-coded) reserved. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 00h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 121 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.9.6. dmic0 (nid = 0eh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 122 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 3h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 123 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 4h por default assocation. sequence 3:0 rw 0h por sequence. 7.10. dmic1 (nid = 0fh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 124 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 125 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.10.1. dmic1 (nid = 0fh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 126 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hphndrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.10.2. dmic1 (nid = 0fh): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 127 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.10.3. dmic1 (nid = 0fh): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.10.4. dmic1 (nid = 0fh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 128 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.10.5. dmic1 (nid = 0fh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:6 r 0000000h n/a (hard-coded) reserved. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 00h n/a (hard-coded) reserved. 7.10.6. dmic1 (nid = 0fh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 129 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset portconnectivity 31:30 rw 1h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 00h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw fh por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 130 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connectiontype 19:16 rw 0h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw fh por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 131 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.11. dac0 (nid = 10h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 132 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.11.1. dac0 (nid = 10h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 133 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.11.2. dac0 (nid = 10h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 134 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.11.3. dac0 (nid = 10h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.11.4. dac0 (nid = 10h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 135 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.11.5. dac0 (nid = 10h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 136 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.11.6. dac0 (nid = 10h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 7.12. dac1 (nid = 11h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 137 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 138 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.12.1. dac1 (nid = 11h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 139 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.12.2. dac1 (nid = 11h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.12.3. dac1 (nid = 11h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 140 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.12.4. dac1 (nid = 11h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 141 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.12.5. dac1 (nid = 11h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 7.12.6. dac1 (nid = 11h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 142 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.13. adc0 (nid = 12h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 143 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.13.1. adc0 (nid = 12h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 144 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.13.2. adc0 (nid = 15h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 14h n/a (hard-coded) adc0mux selector widget (0x14) 7.13.3. adc0 (nid = 15h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 145 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.13.4. adc0 (nid = 12h): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 146 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 7.13.5. adc0 (nid = 12h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 147 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.13.6. adc0 (nid = 12h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 7.14. adc1 (nid = 13h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 148 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 149 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.14.1. adc1 (nid = 13h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.14.2. adc1 (nid = 13h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 150 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 15h n/a (hard-coded) adc1mux widget (0x18) 7.14.3. adc1 (nid = 13h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 151 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.14.4. adc1 (nid = 13h): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 152 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 7.14.5. adc1 (nid = 13h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 153 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.14.6. adc1 (nid = 1bh): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 7.15. adc0mux (nid = 14h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 154 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 155 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.15.1. adc0mux (nid = 14h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 05h n/a (hard-coded) number of nid entries in connection list 7.15.2. adc0mux (nid = 14h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) unused list entry. conl5 15:8 r 00h n/a (hard-coded) unused list entry. conl4 7:0 r 0fh n/a (hard-coded) dmic 1 widget (0x0f) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 156 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.15.3. adc0mux (nid = 14h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 0eh n/a (hard-coded) dmic 0 widget (0x0e) conl2 23:16 r 11h n/a (hard-coded) dac1 widget (0x11) conl1 15:8 r 10h n/a (hard-coded) dac0 widget (0x10) conl0 7:0 r 16h n/a (hard-coded) portmux widget (0x16) 7.15.4. adc0mux (nid = 14h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 03h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 157 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec numsteps 14:8 r 2eh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 10h n/a (hard-coded) indicates which step is 0db 7.15.5. adc0mux (nid = 14h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.15.6. adc0mux (nid = 14h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 158 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.15.7. adc0mux (nid = 14h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 7.15.8. adc0mux (nid = 14h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 159 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.15.9. adc0mux (nid = 14h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 160 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.16. adc1mux (nid = 15h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 161 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.16.1. adc1mux (nid = 15h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 05h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 162 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.16.2. adc1mux (nid = 15h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) unused list entry. conl5 15:8 r 00h n/a (hard-coded) unused list entry. conl4 7:0 r 0fh n/a (hard-coded) dmic 1 widget (0x0f) 7.16.3. adc1mux (nid = 15h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 0eh n/a (hard-coded) dmic 0 widget (0x0e) conl2 23:16 r 11h n/a (hard-coded) dac1 widget (0x11) conl1 15:8 r 10h n/a (hard-coded) dac0 widget (0x10) conl0 7:0 r 16h n/a (hard-coded) portmux widget (0x16) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 163 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.16.4. adc1mux (nid = 15h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 03h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 2eh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 10h n/a (hard-coded) indicates which step is 0db 7.16.5. adc1mux (nid = 15h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 164 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.16.6. adc1mux (nid = 15h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.16.7. adc1mux (nid = 15h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 165 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 7.16.8. adc1mux (nid = 15h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 166 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.16.9. adc1mux (nid = 15h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 7.17. portmux (nid = 16h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 167 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 168 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.17.1. portmux (nid = 16h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 02h n/a (hard-coded) number of nid entries in connection list. 7.17.2. portmux (nid = 16h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) reserved. conl2 23:16 r 00h n/a (hard-coded) reserved. conl1 15:8 r 0bh n/a (hard-coded) portb pin widget (0x0b) conl0 7:0 r 0ch n/a (hard-coded) portc pin widget (0x0c) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 169 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.17.3. portmux (nid = 16h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 0000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 7.17.4. portmux (nid = 16h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 170 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.18. spdifout0 (nid = 17h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 4h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 171 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 1h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.18.1. spdifout0 (nid = 17h): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 172 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 173 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 7.18.2. spdifout0 (nid = 17h): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 1h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 7.18.3. spdifout0 (nid = 17h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 174 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 00h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 00h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 7.18.4. spdifout0 (nid = 17h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. frmtnonpcm 15 rw 0h por - dafg - ulr stream type: 1 = non-pcm, 0 = pcm. 7.18.3. spdifout0 (nid = 17h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 175 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.18.5. spdifout0 (nid = 17h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 176 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.18.6. spdifout0 (nid = 17h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.18.7. spdifout0 (nid = 1dh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 177 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.18.8. spdifout0 (nid = 17h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 178 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.18.9. spdifout0 (nid = 17h): digcnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 73fh 73eh 70eh 70dh get f0e00h / f0d00h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. keepalive 23 rw 0h por - dafg - ulr keep alive enable: 1 = clocking information maintained during d3, 0 = clock information not required during d3. rsvd1 22:15 r 00h n/a (hard-coded) reserved. cc 14:8 rw 00h por - dafg - ulr cc: category code. l 7 rw 0h por - dafg - ulr l: generation level. pro 6 rw 0h por - dafg - ulr pro: professional. audio 5 rw 0h por - dafg - ulr /audio: non-audio. copy 4 rw 0h por - dafg - ulr copy: copyright. pre 3 rw 0h por - dafg - ulr pre: preemphasis. vcfg 2 rw 0h por - dafg - ulr vcfg: validity config. v 1 rw 0h por - dafg - ulr v: validity. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 179 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec digen 0 rw 0h por - dafg - ulr digital enable: 1 = converter enabled, 0 = converter disable. 7.19. dig0pin (nid = 18h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 180 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.19.1. dig0pin (nid = 18h): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 181 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.19.2. dig0pin (nid = 18h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 182 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.19.3. dig0pin (nid = 18h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 17h n/a (hard-coded) spdifout0 converter widget (0x17) 7.19.4. dig0pin (nid = 18h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 183 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.19.5. dig0pin (nid = 18h): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 184 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd1 5:0 r 00h n/a (hard-coded) reserved. 7.19.6. dig0pin (nid = 18h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.19.7. dig0pin (nid = 18h): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 185 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.19.8. dig0pin (nid = 18h): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 1h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 00h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 186 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec device 23:20 rw fh por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 0h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 187 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw fh por default assocation. sequence 3:0 rw 0h por sequence. 7.20. digbeep (nid = 19h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd4 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 188 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec type 23:20 r 7h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined rsvd3 19:11 r 000h n/a (hard-coded) reserved. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no." rsvd2 9:4 r 00h n/a (hard-coded) reserved ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 7.20.1. digbeep (nid = 19h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 189 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 17h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 03h n/a (hard-coded) indicates which step is 0db 7.20.2. digbeep (nid = 19h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:2 r 00h n/a (hard-coded) reserved. gain 1:0 rw 1h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 190 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.20.3. digbeep (nid = 19h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.20.4. digbeep (nid = 19h): gen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ah get f0a00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 191 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. divider 7:0 rw 00h por - dafg - lr enable internal pc-beep generation. divi der == 00h disables internal pc beep generation and enables normal operation of the codec. divider != 00h gener- ates the beep tone on all pin complexes that are currently configured as out- puts. the hd audio spec states that the beep tone frequency = (48khz hd audio sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarith- mic scale). 7.20.5. digbeep (nid = 19h): gain reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 77ah get f7a00h field name bits r/w default reset rsvd 31:3 r 000000h n/a (hard-coded) reserved. divider 2:0 rw 05h por - dafg - lr digital pc beep gain adjust in digital side 0h = -9db, 1h = -6db, 2h = -3db, 3h = 0db, 4h = +3db, 5h = +6db 7.21. advancedfunctions (nid = 1ah): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 192 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec this register is reset by por field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r fh n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 0h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 193 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec all registers are available when in normal mode through the hd audio interface. most are implemented using vendor defined verbs but some (volume controls specifically) are sup- ported through standard verbs at the pin widgets this register is reset by por formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.21.1. advancedfunctions (nid = 1ah): cntrl0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 77?h get f7?00h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) f7?0077?,, please refer to the class-d register description. value 7:0 rw 00h por - dafg - ulr control register value of i2c module. 7.21.2. advancedfunctions (nid = 1ah): cntrl1 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 78?h get f8?00h field name bits r/w default reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 194 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec this register is reset by por this register is reset by por this register is reset by por field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) f8?0078?,, please refer to the class-d register description. value 7:0 rw 00h por - dafg - ulr control register value of i2c module. 7.21.3. advancedfunctions (nid = 1ah): cntrl2 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 79?h get f9?00h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) f9?0079?,, please refer to the class-d register description. value 7:0 rw 00h por - dafg - ulr control register value of i2c module. 7.21.4. advancedfunctions (nid = 1ah): cntrl3 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7a?h get fa?00h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) fa?007a?,, please refer to the class-d register description. value 7:0 rw 00h por - dafg - ulr control register value of i2c module. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 195 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.1. spkvol l/r registers. note: register values reset by por or by writing to the reset register. 7.21.4.2. pwrm register note: register values reset by por or by writing to the reset register. 7.21.4.3. reset register register address bit label type default description verb f71/771 (left) verb f72/772 (right) verb 773 (left and right - write only) 7:0 vol[7:0] rw 30 +36 to -91.5db in 0.75db steps 0x00 = +36db 0x01 = +35.25db ... 0x2f = +0.75db 0x30 = 0db 0x31 = -0.75db ... 0xa9 = -90.75 0xaa to 0xfe = -91.5db 0xff = mute register address bit label type default description verb f79/779 7 rsvd ro 0 reserved 6 rsvd ro 0 reserved 5 rsvd ro 0 reserved 4 hppwd rw 0 reserved 3 spkron rw 0 reserved 2 dmicpwd rw 0 reserved 1 rsvd ro 1 reserved 0 auxen ro 0 reserved register address bit label type default description verb f7f/77f 7:0 reset rw 0 writing causes registers to revert to their default values (similar to a function group reset). eqram contents (eq coefficients and eq prescale) are not affected. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 196 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.4. status register note: register values reset by por or by writing to the reset register. 7.21.4.5. init register note: register values reset by por or by writing to the reset register. 7.21.4.6. config register note: register values reset by por or by writing to the reset register. register address bit label type default description verb f80/780 7 limit1latch ro 0 latched version of limit1, clear via gainctrl_lo[7] 6 limit0latch ro 0 latched version of limit0, clear via gainctrl_lo[7] 5:3 reserved ro 0x0 reserved 2 limit1 ro 0 set (1) if regz saturation afte r gain multiply for ch1. may change on a sample by sample basis. 1 limit0 ro 0 set (1) if regz saturation afte r gain multiply for ch0. may change on a sample by sample basis. 0 zerodet_flag ro 0 set when input zero detect of long string of zeroes. register address bit label type default description verb f81/781 7:4 reserved ro 0 reserved 3 anabeep_dcbyp rw 0 1 = bypass analog beep dc filter 2:1 anabeep_dc_coef f rw 0x2 0: dc_coef = 24?h004000; 1: dc_coef = 24?h001000; 2: dc_coef = 24?h000400; 3: dc_coef = 24?h000100; 0 initialize rw 0 1= initialize/soft reset data path. must be set when changing the config0 or config1 registers. register address bit label type default description verb f82/782 7 rsvd rw 0 reserved 6 prebyp rw 1 1= bypass btl eq filter prescale 5 eqbyp rw 1 1= bypass btl eq filter 4:1 reserved rw 0 reserved 0 hpfbyp ro 0 1= bypass btl high-pass filter (not dc removal filter) www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 197 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.7. pwm4 register. note: register values reset by por or by writing to the reset register. 7.21.4.8. pwm3 register note: register values reset by por or by writing to the reset register. 7.21.4.9. pwm2 register note: register values reset by por or by writing to the reset register. register address bit label type default description verb f83/783 7 sc_status_clear_right rwc 0 write once o peration will clear sc_fault_status_right 6 sc_status_clear_left rwc 0 write once o peration will clear sc_fault_status_left 5 reserved ro 0 reserved 4 sc_fault_status_right ro 0 1 = fault occurs on right channel 3 sc_fault_status_left ro 0 1 = fault occurs on left channel 2:1 scdly_set rw 00 used for short circuit detection; designer will set the value 0 evenbit rw 0 1=noise shaper output data are even register address bit label type default description verb f84/784 7:6 outctrl rw 0 pwm output muxing 0 = normal 1 = swap 0/1 2 = ch0 on both 3 = ch1 on both 5:0 cvalue rw 0x2 tristate constant value filed, must be even and not 0 register address bit label type default description verb f85/785 7:2 dvalue rw 0x10 dvalue constant field. 1 pwm_outflip rw 0 1= swap pwm a/b output pair for all channels 0 pwm_outmode rw 1 1= tristate, 0 = binary www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 198 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.10. pwm1register note: register values reset by por or by writing to the reset register. 7.21.4.11. pwm0 register note: register values reset by por or by writing to the reset register. register address bit label type default description verb f86/786 7 reserved ro 0 reserved 6:2 dithpos rw 0 dither position, where dither inserted after ns 0,1,2 = dither bits 2:0 4 = dither bits 3:1 5 = dither bits 4:1 ... 19 = dither bits 19:17 1 dither_range rw 0 1= dither -1 to +1, 0 = dither -3 to +3 0 dithclr rw 0 1 = disable dither register address bit label type default description verb f87/787 7:6 phaseoffset rw 01 pwm ch1 offset from ch0 at 8x sample rate by: 00 = 0 degrees 01 = 90 degrees 10 = 180 degrees 11 = na 5 clk320mode r 1 1 = pca clock 320 mode 0 = pca clock 294 mode 4 roundup rw 1 1= roundup, 0 = truncate for quantizer 3 bfclr rw 0 1 = disable binomial filter 2 fourthorder rw 0 1 = fourth order binomial filter, 0 = 3rd order binomial filter 1 add3_sel rw 0 1 = 24-bit noise shaper output (pre-quantizer), 0 = 8/9/10-bit quantizer output 0 btl_test_mode rw 0 1 = power stage test mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 199 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.12. lmtctrl register control operation of the volume limiter (compressor). note: register values reset by por or by writing to the reset register. 7.21.4.13. lmtatktime (0x19), lmtholdtime (0x1a), lmtreltime (0x1b) registers these 8-bit registers set the timer values between incrementi ng/decrementing the compressor attenuation values. there is one register each for attack, hold, and release times, the configuration parameters are the same for all three and are shown in the table below.. note: register values reset by por or by writing to the reset register. 7.21.4.14. lmtatkth (0x1d?lo, 0x1c?hi), lmtrelth (0x1f?lo, 0x1e?hi) registers these 16-bit registers set the threshold values. when in attack phase and the attack threshold is exceeded the compressor attenuation is incremented by stepsize (see lm tctrl). when in release phase and the release threshold is not exceeded the compressor attenuation is incr emented by stepsize (but not above 0).. register address bit label type default description verb f88/788 7:4 ? ro 0 reserved for future use. 3 zerocross rw 0 1 = only change limiter gain value on zero cross. 2:1 stepsize rw 0 gain stepsize when incrementing or decrementing: 0 - 0.75 db, 1 - 1.5 db, 2 - 3.0 db, 3 - 6.0 db 0 limiter_en rw 0 1 = enable limiter (compressor) register address bit label type default description verb f89/789 7 atk10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtat[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description verb f8a/78a 7 hold10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtht[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description verb f8b/78b 7 rel10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtrt[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description verb f8c/78c 7:0 latkth[15:8] rw 7f 8?hff would equal threshold level of +2.0db. each step below this 8-bit full scale value reduces threshold level by 0.0078 db. register address bit label type default description verb f8d/78d 7:0 latkth[7:0] rw ff always 0. it isn?t necessary to provide threshold resolution to the point where these lower 8 bits would be used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 200 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.15. gainctrl_hi register. note: register values reset by por or by writing to the reset register. 7.21.4.16. gainctrl_lo register. note: register values reset by por or by writing to the reset register. register address bit label type default description verb f8e/78e 7:0 lrelth[15:8] rw 0 8?hff would equal threshold level of +2.0db. each step below this 8-bit full scale value reduces threshold level by 0.0078 db. register address bit label type default description verb f8f/78f 7:0 lrelth[7:0] rw 0 always 0. it isn?t necessary to provide threshold resolution to the point where these lower 8 bits would be used. register address bit label type default description verb f90/790 7:5 reserved ro 0 reserved 4:3 zerodetlen rw 0x2 enable mute if input consecutive zeros exceeds this length: 00 = 32 01 = 1000 10 = 2000 11 = 4000 2:0 step_time rw 0x5 step time units = 1< idt confidential 201 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.17. mute register. note: register values reset by por or by writing to the reset register. 7.21.4.18. atten register. note: register values reset by por or by writing to the reset register. 7.21.4.19. dc_coef_sel register note: register values reset by por or by writing to the reset register. register address bit label type default description verb f92/792 7:3 reserved ro 0x0 reserved 2 mute rw 0 1 = mute all channels 1 mute1 rw 0 1 = mute ch1 0 mute0 rw 0 1 = mute ch0 register address bit label type default description verb f93/793 7:0 atten rw 0x0 attenuation. each bit represen ts 0.5db of attenuation to be applied to the channel. the range will be -125db to 2db as follows: 0x00: +2db 0x01: +1.5db 0x02: +1.0db ... 0x47: -33.5db 0x48: -34.0db 0x49: -34.5db ... 0xfe: -125db 0xff: hard master mute register address bit label type default description verb f94/794 7:3 reserved ro 0 reserved 2:0 dc_coef_sel rw 0x5 0:dc_coef = 24?h100000; //2^^-3 = 0.125 1:dc_coef = 24?h040000; 2:dc_coef = 24?h010000; 3:dc_coef = 24?h004000; 4:dc_coef = 24?h001000; 5:dc_coef = 24?h000400; 6:dc_coef = 24?h000100; //2^^-15 = 0.000330517 7:dc_coef = 24?h000040; //2^^-17 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 202 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.20. btl high-pass filter coef_sel register. note: register values reset by por or by writing to the reset register. 7.21.4.21. btl class-d power stage register settings . register address bit label type default description verb f95/795 7:3 reserved ro 0 reserved 2:0 hp_coef_sel rw 0x2 select iir coefficients for btl amplifier high pass filter corner frequency 000 = 100hz 001 = 200hz 010 = 300hz 011 = 400hz 100 = 500hz 101 = 750hz 110 = 1000hz 111 = 2000hz register address bit label type default description verb f97/797 7 enable rw 1 1 = enable btl power stage 6 trc_esd ro 0 1 = esd trigger detected 0 = no trigger 5 strendrv rw 0 1 = strengthen pre-drive 0 = normal 4:3 scthr rw 01 short circuit th reshold current 00 = 10% of pvdd 01 = 14% of pvdd 10 = 16% of pvdd 11 = 20% of pvdd 2:0 deadtime rw 001 dead time for output fets 000 = 0.5ns 001 = 1.0ns 010 = 1.5ns 011 = 2ns 100 = 4ns 101 = 8ns 110 = 8ns 111 = 8ns www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 203 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec register address bit label type default description verb f98/798 7 test_en rw 0 1 = enable short circuit test 6 sc_dis rw 0 1 = disable short circuit protection 5 rsvd rw 0 reserved 4 fault_sc ro 0 1 = fault 3 rsvd rw 0 reserved 2 pnsel rw 0 1=pfet tested, 0=nfet tested 1 force_sc rw 0 1 = force short circuit 0 test rw 0 1 = pos pfet / neg nfet on, 0 = pos nfet / neg pfet on register address bit label type default description verb f99/799 7 enable rw 1 1 = enable btl power stage 6 trc_esd ro 0 1 = esd trigger detected 0 = no trigger 5 strendrv rw 0 1 = strengthen pre-drive 0 = normal 4:3 scthr rw 01 short circuit threshold current 00 = 10% of pvdd 01 = 14% of pvdd 10 = 16% of pvdd 11 = 20% of pvdd 2:0 deadtime rw 001 dead time for output fets 000 = 0.5ns 001 = 1.0ns 010 = 1.5ns 011 = 2ns 100 = 4ns 101 = 8ns 110 = 8ns 111 = 8ns register address bit label type default description verb f9a/79a 7 test_en rw 0 1 = enable short circuit test 6 sc_dis rw 0 1 = disable short circuit protection 5 rsvd rw 0 reserved 4 fault_sc ro 0 1 = fault 3 rsvd rw 0 reserved 2 pnsel rw 0 1=pfet tested, 0=nfet tested 1 force_sc rw 0 1 = force short circuit 0 test rw 0 1 = pos pfet / neg nfet on, 0 = pos nfet / neg pfet on www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 204 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec note: register values reset by por or by writing to the reset register. 7.21.4.22. ldo level control register. note: register values reset by por only. 7.21.4.23. eqram the eq ram is a 52 x 48-bit sram that contains the eq coefficients.. register address bit label type default description verb f9b/79b 7:3 reserved ro 0x0 reserved 2 lv_quad_bias ro 0 reserved 1:0 lv_reg_cntrl_bit rw 0x0 two bits are defined to program the output of the 1.8v ldo 00 = normal operation (3.3v in to 1.8v out) 01 = 1.8v*1.1 = 1.98v 10 = 1.8v*0.9 = 1.62v 11 = power down ldo/bypass. when disabled, the dvdd_core pin must be supplied with a nominal 1.8v from an external source. address channel right coefficients (24bit ) channel left coefficients (24bit) eqram bits [47:24] [23:00] based on 44.1khz sample rate 0x00 eq_coef_f0_b0 eq_coef_f0_b0 0x01 eq_coef_f0_b1 eq_coef_f0_b1 0x02 eq_coef_f0_b2 eq_coef_f0_b2 0x03 eq_coef_f0_a1 eq_coef_f0_a1 0x04 eq_coef_f0_a2 eq_coef_f0_a2 0x05 eq_coef_f1_b0 eq_coef_f1_b0 0x06 eq_coef_f1_b1 eq_coef_f1_b1 0x07 eq_coef_f1_b2 eq_coef_f1_b2 0x08 eq_coef_f1_a1 eq_coef_f1_a1 0x09 eq_coef_f1_a2 eq_coef_f1_a2 0x0a eq_coef_f2_b0 eq_coef_f2_b0 0x0b eq_coef_f2_b1 eq_coef_f2_b1 0x0c eq_coef_f2_b2 eq_coef_f2_b2 0x0d eq_coef_f2_a1 eq_coef_f2_a1 0x0e eq_coef_f2_a2 eq_coef_f2_a2 0x0f eq_coef_f3_b0 eq_coef_f3_b0 0x10 eq_coef_f3_b1 eq_coef_f3_b1 0x11 eq_coef_f3_b2 eq_coef_f3_b2 0x12 eq_coef_f3_a1 eq_coef_f3_a1 0x13 eq_coef_f3_a2 eq_coef_f3_a2 0x14 eq_coef_f4_b0 eq_coef_f4_b0 0x15 eq_coef_f4_b1 eq_coef_f4_b1 0x16 eq_coef_f4_b2 eq_coef_f4_b2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 205 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec the eqram is programmed indirectly through the control bus in the following manner: 1) write the 48-bit write data to the eqram_write register 2) write the target addre ss to the eq_address register 3) set bit 7 of the eqram_ctrl register the write will occur when the eqram is not being access ed by the dsp audio proce ssing routines. when complete the hardware will automa tically clear this bit. reading back from the eqram is done in the following manner: 1) write target address to eq_addr register 2) set bit 6 of the eqram_ctrl register when the hardware comple tes the read it will automa tically clear this bit. 3) when bit 6 of the eqram_ctrl register has been cleare d, read the 48bit data from the eqram_read register. 0x17 eq_coef_f4_a1 eq_coef_f4_a1 0x18 eq_coef_f4_a2 eq_coef_f4_a2 0x19 eq_prescale eq_prescale based on 48khz sample rate 0x1a eq_coef_f0_b0 eq_coef_f0_b0 0x1b eq_coef_f0_b1 eq_coef_f0_b1 0x1c eq_coef_f0_b2 eq_coef_f0_b2 0x1d eq_coef_f0_a1 eq_coef_f0_a1 0x1e eq_coef_f0_a2 eq_coef_f0_a2 0x1f eq_coef_f1_b0 eq_coef_f1_b0 0x20 eq_coef_f1_b1 eq_coef_f1_b1 0x21 eq_coef_f1_b2 eq_coef_f1_b2 0x22 eq_coef_f1_a1 eq_coef_f1_a1 0x23 eq_coef_f1_a2 eq_coef_f1_a2 0x24 eq_coef_f2_b0 eq_coef_f2_b0 0x25 eq_coef_f2_b1 eq_coef_f2_b1 0x26 eq_coef_f2_b2 eq_coef_f2_b2 0x27 eq_coef_f2_a1 eq_coef_f2_a1 0x28 eq_coef_f2_a2 eq_coef_f2_a2 0x29 eq_coef_f3_b0 eq_coef_f3_b0 0x2a eq_coef_f3_b1 eq_coef_f3_b1 0x2b eq_coef_f3_b2 eq_coef_f3_b2 0x2c eq_coef_f3_a1 eq_coef_f3_a1 0x2d eq_coef_f3_a2 eq_coef_f3_a2 0x2e eq_coef_f4_b0 eq_coef_f4_b0 0x2f eq_coef_f4_b1 eq_coef_f4_b1 0x30 eq_coef_f4_b2 eq_coef_f4_b2 0x31 eq_coef_f4_a1 eq_coef_f4_a1 0x32 eq_coef_f4_a2 eq_coef_f4_a2 0x33 eq_prescale eq_prescale address channel right coefficients (24bit ) channel left coefficients (24bit) eqram bits [47:24] [23:00] www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 206 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 7.21.4.24. eqram read data (0x30?0x35), eqram write data (0x36?3b) registers these two 48-bit registers (addressed as 12 8-bit registers) are 48-bit data holding registers used- when doing indirect writes/reads to the eqram..]] register address bit label type default description eqram_read[47:40] verb fa0/7a0 7:0 eqrd[47:40] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_read[39:32] verb fa1/7a1 7:0 eqrd[39:32] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_read[31:24] verb fa2/7a2 7:0 eqrd[31:24] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_read[23:16] verb fa3/7a3 7:0 eqrd[23:16] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_read[15:8] verb fa4/7a4 7:0 eqrd[15:8] rw 0x00 48-bit data register, contains t he contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_read[7:0] verb fa5/7a5 7:0 eqrd[7:0] rw 0x00 48-bit data register, contains th e contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description eqram_write[47:40] verb fa6/7a6 7:0 eqwd[47:40] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description eqram_write[39:32] verb fa7/7a7 7:0 eqwd[39:32] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written w ill have be specified by the eqram address fields. www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 207 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec note: register values reset by por or by writing to the reset register. 7.21.4.25. eqram address register this 8-bit register provides the add ress to the internal ram when doing indirect writes/reads to the eqram.. note: register values reset by por or by writing to the reset register. 7.21.4.26. eqram control register this control register provides the write/read enabl e when doing indirect writes/reads to the eqram. note: register values reset by por or by writing to the reset register. register address bit label type default description eqram_write[31:24] verb fa8/7a8 7:0 eqwd[31:24] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description eqram_write[23:16] verb fa9/7a9 7:0 eqwd[23:16] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written w ill have be specified by the eqram address fields. register address bit label type default description eqram_write[15:8] verb faa/7aa 7:0 eqwd[15:8] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description eqram_write[7:0] verb fab/7ab 7:0 eqwd[7:0] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description verb fac/7ac 7:6 rsvd ro 0x00 reserved 5:0 eqadd[5:0] rw 0x00 contains the address (between 0x00 and 0x33) of the eqram to be accessed by a read or write. this is not a byte address--it is the address of the 48-bit data item to be accessed from the eqram. register address bit label type default description verb fad/7ad 7 eqram_wr rw 0 1 = write to eqram, cleared by hw when done 6 eqram_rd rw 0 1 = read from eqram, cleared by hw when done 5:0 rsvd ro 0 reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 208 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 8. pinout and packaging figure 15. 40-qfn pin assignment 40-qfn dvdd_lv sdata_out bitclk sdata_in dvdd* sync 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 13 14 21 22 23 24 25 26 27 28 29 30 38 37 36 35 34 33 32 31 40 39 sense_a portc_l portc_r vrefout_b vrefout_c vreffilt fcap2 vpos avdd1 porta_r porta_l eapd pvdd dmic_clk/gpio 1 dmic_0/gpio 2 fcap1 portd_+r portd_-r portd_-l portd_+l pvss pvdd spdif/gpio3 pc_beep portb_l portb_r cpvreg avdd2 dvddio vneg pvss dmic_1/gpio 0 reset# cap2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 209 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 8.0.1. 40-qfn pin table pin name pin function i/o internal pull-up/pull-down 40 pin location dvdd_lv 1.8v digital core regulat or filter cap o(digital) none 1 dmic_clk/gpio1 digital mic clock out put/gpio1 i/o(digital) 60k pull-down 2 dmic0/gpio2 digital mic 01 input/gpio2 i/o(digital) 60k pull-down 3 dmic1/gpio0 digital mic 23 input/gpio0 i/o(digital) 60k pull-down 4 sdata_out hd audio serial data output from controller i/o(digital) none 5 bitclk hd audio bit clock i(digital) none 6 dvdd_io hd audio bus signal level 3.3v or 1.5v i(digital) none 7 sdata_in hd audio serial data input to controller o(digital) none 8 dvdd digital vdd= 3.3v i(digital) none 9 sync hd audio frame sync i(digital) none 10 reset# hd audio reset i(digital) none 11 pcbeep pc beep i(analog) none 12 sense_a jack insertion detection ports a,b,c i(analog) none 13 portc_l port c left i(analog) none 14 portc_r port c right i(analog) none 15 vrefout-c port c microphone bias o(analog) none 16 portb_l port b left i(analog) none 17 portb_r port b right i(analog) none 18 vrefout-b port b microphone bias o(analog) none 19 vreffilt analog virtual ground o(analog) none 20 cap2 reference filter cap o(analog) none 21 avdd1 analog vdd= 3.3v i(analog) none 22 porta_l port a output left o(analog) none 23 porta_r port a output right o(analog) none 24 vpos positive headphone supply o(analog) none 25 vneg negative headphone supply o(analog) none 26 fcap2 charge pump flying cap o(analog) none 27 fcap1 charge pump flying cap o(analog) none 28 cpvreg linear regulator output filter cap o(analog) none 29 avdd2 analog supply for vreg i(analog) none 30 pvdd analog supply for class-d amp i(analog) none 31 portd_+l btl amp left + o(analog) none 32 portd_-l btl amp left - o(analog) none 33 pvss analog ground i(analog) none 34 pvss analog ground i(analog) none 35 portd_-r btl amp right - o(analog) none 36 portd_+r btl amp right + o(analog) none 37 table 31. 40qfn pin description www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 210 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 8.0.2. 40-qfn package outline and package dimensions package dimensions are kept curr ent with jedec publication no. 95 figure 16. 40-qfn package diagram pvdd analog supply for class-d amp i(analog) none 38 eapd eapd i/o (digital) 60k pull-up 39 spdifout/gpio3 spdif output or gpio3 i/o (digital) 60k pull-down 40 pin name pin function i/o internal pull-up/pull-down 40 pin location table 31. 40qfn pin description www.datasheet.net/ datasheet pdf - http://www..co.kr/
idt confidential 211 v 0.91 06/12 ?2012 integrated device technology, inc. 92HD95 92HD95 four channel hd audio codec 8.1. standard reflow profile data note: these devices can be hand soldered at 360 o c for 3 to 5 seconds. from: ipc / jedec j-std-020c ?moisture/reflow se nsitivity classification for nonhermetic solid state surface mount devices? (www.jedec.org/download). profile feature pb free assembly average ramp-up rate (ts max - tp) 3 o c / second max preheat: temperature min (ts min ) temperature max (ts max ) time (ts min - ts max ) 150 o c 200 o c 60 - 180 seconds time maintained above: temperature (t l ) time (t l ) 217 o c 60 - 150 seconds peak / classification temperature (tp) see ?package classification reflow temperatures? time within 5 o c of actual peak temper ature (tp) 20 - 40 seconds ramp-down rate 6 o c / second max time 25 o c to peak temperature 8 minutes max note: all temperatures refer to topside of the package, measured on the package body surface. table 32. standard reflow profile www.datasheet.net/ datasheet pdf - http://www..co.kr/
92HD95 four channel hd audio codec 6024 silver creek valley road san jose, california 95138 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to mo dify the products and/or specif ications de- scribed herein at any time and at idt?s sole discretion. all in formation in this document, including descriptions of product fe atures and perfor- mance, is subject to change without notice. performance specifications and the operati ng parameters of the described products a re determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the information co ntained herein is provided without repres entation or warranty of any kind, whether express or implied, including, but not limited to, t he suitability of idt?s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the intellectual property r ights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other tra demarks and service marks used he rein, in- cluding protected names, logos and desi gns, are the property of idt or thei r respective third party owners. 9. disclaimer while the information pres ented herein has been checke d for both accuracy and relia bility, manufacturer assumes no responsibility for either its use or for t he infringement of any patent s or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are im plied. this product is intend ed for use in normal commercial applications. any other applications, such as those re quiring extended temper ature range, high reliability, or other extraordinary environmental requirements, are not recommended without additional proces sing by manufacturer. man- ufacturer reserves the right to change any circuitry or spec ifications without notice. manufacturer does not authorize or warrant any product for use in life support devices or critical medical instruments. 10. document revision history revision date description of change 0.5 january 2012 initial release 0.6 april 2012 updated config defaults, added rtd3 support 0.9 april 2012 widget details added. 0.91 june 2012 added thd+n setting to class d output power and 3w typical line. www.datasheet.net/ datasheet pdf - http://www..co.kr/

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